公开(公告)号：US20190164977A1

公开(公告)日：2019-05-30

申请号：US16226648

申请日：2018-12-20

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Kuan-Chun Lin ,  Chi-Mao Hsu ,  Shu-Yen Chan ,  Shih-Fang Tzou ,  Tsuo-Wen Lu ,  Tien-Chen Chan ,  Feng-Yi Chang ,  Shih-Kuei Yen ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L21/28

Abstract: A method of fabricating a buried word line structure includes providing a substrate with a word line trench therein. Two source/drain doped regions are disposed in the substrate at two sides of the word line trench. Later, a silicon oxide layer is formed to cover the word line trench. A titanium nitride layer is formed to cover the silicon oxide layer. Next, a tilt ion implantation process is performed to implant silicon atoms into the titanium nitride layer to transform part of the titanium nitride layer into a titanium silicon nitride layer. A conductive layer is formed in the word line trench. Subsequently, part of the conductive layer, part of the titanium silicon nitride layer and part of the silicon oxide layer are removed to form a recess. Finally, a cap layer fills in the recess.

公开(公告)号：US10236294B2

公开(公告)日：2019-03-19

申请号：US15854827

申请日：2017-12-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chien-Ting Ho ,  Shih-Fang Tzou ,  Chun-Yuan Wu ,  Li-Wei Feng ,  Yu-Chieh Lin ,  Ying-Chiao Wang ,  Tsung-Ying Tsai

IPC: H01L27/105 ,  H01L21/768 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3105

Abstract: The present invention proposes a method of manufacturing a semiconductor device, which includes the steps of providing a substrate with a memory region and a logic region, forming bit lines and logic gates respectively in the memory region and the logic region, wherein storage node regions are defined between bit lines, forming a first low-K dielectric layer on sidewalls of bit lines, forming a doped silicon layer in the storage node regions between bit lines, wherein the top surface of doped silicon layer is lower than the top surface of bit line, forming a second low-K dielectric layer on sidewalls of storage node regions, and filling up storage node regions with metal plugs.

公开(公告)号：US20190074280A1

公开(公告)日：2019-03-07

申请号：US15951194

申请日：2018-04-12

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Tien-Chen Chan ,  Shu-Yen Chan ,  Chi-Mao Hsu ,  Shih-Fang Tzou ,  Ting-Pang Chung ,  Chia-Wei Wu

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/48 ,  H01L21/762 ,  H01L21/324

CPC classification number: H01L27/10873 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02576 ,  H01L21/324 ,  H01L21/4814 ,  H01L21/762

Abstract: A method of manufacturing a semiconductor device is provided, which includes the steps of providing a capacitor structure, forming a conductive layer on the capacitor structure, performing a hydrogen doping process to the conductive layer, forming a metal layer on the conductive layer after the hydrogen doping process, and patterning the metal layer and the conductive layer to forma top electrode plate.

公开(公告)号：US10170362B2

公开(公告)日：2019-01-01

申请号：US15472295

申请日：2017-03-29

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Shih-Fang Tzou ,  Yu-Cheng Tung ,  Fu-Che Lee ,  Ming-Feng Kuo

IPC: H01L23/52 ,  H01L21/768 ,  H01L21/762 ,  H01L21/311 ,  H01L21/02 ,  H01L23/535 ,  H01L29/06 ,  H01L23/528 ,  H01L27/108

Abstract: The present invention provides a method of forming a semiconductor device. First, providing a substrate, and an STI is forming in the substrate to define a plurality of active regions. Then a first etching process is performed to form a bit line contact opening, which is corresponding to one of the active regions. A second etching process is performed to remove a part of the active region and its adjacent STI so a top surface of active region is higher than a top surface of the STI. Next, a bit line contact is formed in the opening. The present invention further provides a semiconductor structure.

公开(公告)号：US20180190656A1

公开(公告)日：2018-07-05

申请号：US15854827

申请日：2017-12-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chien-Ting Ho ,  Shih-Fang Tzou ,  Chun-Yuan Wu ,  Li-Wei Feng ,  Yu-Chieh Lin ,  Ying-Chiao Wang ,  Tsung-Ying Tsai

IPC: H01L27/105 ,  H01L21/768 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L27/1052 ,  H01L21/02532 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76879 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/1085 ,  H01L27/10894 ,  H01L29/6653 ,  H01L29/6656

Abstract: The present invention proposes a method of manufacturing a semiconductor device, which includes the steps of providing a substrate with a memory region and a logic region, forming bit lines and logic gates respectively in the memory region and the logic region, wherein storage node regions are defined between bit lines, forming a first low-K dielectric layer on sidewalls of bit lines, forming a doped silicon layer in the storage node regions between bit lines, wherein the top surface of doped silicon layer is lower than the top surface of bit line, forming a second low-K dielectric layer on sidewalls of storage node regions, and filling up storage node regions with metal plugs.

公开(公告)号：US20180190488A1

公开(公告)日：2018-07-05

申请号：US15859750

申请日：2018-01-02

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Mei-Ling Chen ,  Wei-Hsin Liu ,  Yi-Wei Chen ,  Ching-Hsiang Chang ,  Jui-Min Lee ,  Chia-Lung Chang ,  Tzu-Chin Wu ,  Shih-Fang Tzou

IPC: H01L21/02

CPC classification number: H01L21/02532 ,  H01L21/02422 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02664

Abstract: The present invention provides a method for forming an amorphous silicon multiple layer structure, the method comprises the flowing steps: first, a substrate material layer is provided, next, a first amorphous silicon layer is formed on the substrate material layer, wherein the first amorphous silicon layer includes a plurality of hydrogen atoms disposed therein, afterwards, an UV curing process is performed to the first amorphous silicon layer, so as to remove the hydrogen atoms from the first amorphous silicon layer, finally, a second amorphous silicon layer is formed on the first amorphous silicon layer.

公开(公告)号：US09887088B1

公开(公告)日：2018-02-06

申请号：US15452743

申请日：2017-03-08

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Shih-Fang Tzou ,  Fu-Che Lee ,  Ming-Feng Kuo ,  Li-Chiang Chen

IPC: H01L21/28 ,  H01L21/3213

CPC classification number: H01L21/28088 ,  H01L21/32135

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region defined thereon; forming a trench in the substrate; forming a barrier layer in the trench; forming a conductive layer on the barrier layer; performing a first etching process to remove part of the conductive layer; and performing a second etching process to remove part of the barrier layer. Preferably, the second etching process comprises a non-plasma etching process.

公开(公告)号：US09299843B2

公开(公告)日：2016-03-29

申请号：US14078701

申请日：2013-11-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jun-Jie Wang ,  Po-Chao Tsao ,  Ming-Te Wei ,  Shih-Fang Tzou

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A semiconductor structure comprises a substrate, a plurality of fins, an oxide layer and a gate structure. The fins protrude from the substrate and are separated from each other by the oxide layer. The surface of the oxide layer is uniform and even plane. The gate structure is disposed on the fins. The fin height is distance between the top of the fins and the oxide layer, and at least two of the fins have different fin heights.

Abstract translation: 半导体结构包括基板，多个翅片，氧化物层和栅极结构。 翅片从衬底突出并且通过氧化物层彼此分离。 氧化物层的表面均匀均匀。 栅极结构设置在翅片上。 翅片高度是翅片的顶部和氧化物层之间的距离，并且至少两个翅片具有不同的翅片高度。

公开(公告)号：US20160071800A1

公开(公告)日：2016-03-10

申请号：US14513230

申请日：2014-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Tsung-Hung Chang ,  Yi-Hui Lee ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Chia Chang Hsu ,  Hsin-Fu Huang ,  Chun-Yuan Wu ,  Shih-Fang Tzou

IPC: H01L23/535 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure including a dielectric layer, a titanium layer, a titanium nitride layer and a metal is provided. The dielectric layer is disposed on a substrate, wherein the dielectric layer has a via. The titanium layer covers the via, wherein the titanium layer has tensile stress lower than 1500 Mpa. The titanium nitride layer conformally covers the titanium layer. The metal fills the via. The present invention also provides a semiconductor process for forming said semiconductor structure. The semiconductor process includes the following steps. A dielectric layer is formed on a substrate, wherein the dielectric has a via. A titanium layer conformally covers the via, wherein the titanium layer has compressive stress lower than 500 Mpa. A titanium nitride layer is formed to conformally cover the titanium layer. A metal fills the via.

Abstract translation: 提供了包括电介质层，钛层，氮化钛层和金属的半导体结构。 电介质层设置在基板上，其中介电层具有通孔。 钛层覆盖通孔，其中钛层具有低于1500Mpa的拉伸应力。 氮化钛层共形地覆盖钛层。 金属填充通孔。 本发明还提供了一种用于形成所述半导体结构的半导体工艺。 半导体工艺包括以下步骤。 介电层形成在基板上，其中电介质具有通孔。 钛层保形地覆盖通孔，其中钛层具有低于500Mpa的压应力。 形成氮化钛层以保形地覆盖钛层。 金属填充通孔。

公开(公告)号：US20160027892A1

公开(公告)日：2016-01-28

申请号：US14852624

申请日：2015-09-13

Applicant: United Microelectronics Corp.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Shih-Fang Tzou ,  Chien-Ting Lin ,  Yi-Wei Chen ,  Shi-Xiong Lin ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Hsiao-Pang Chou ,  Chia-Lin Lu

IPC: H01L29/49 ,  H01L29/423 ,  H01L27/088

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823456 ,  H01L21/82385 ,  H01L27/088 ,  H01L29/4232 ,  H01L29/517 ,  H01L29/66545

Abstract: The metal gate structure includes at least a substrate, a dielectric layer, first and second trenches, first metal layer and second metal layers, and two cap layers. In particular, the dielectric layer is disposed on the substrate, and the first and second trenches are disposed in the dielectric layer. The width of the first trench is less than the width of the second trench. The first and second metal layers are respectively disposed in the first trench and the second trench, and the height of the first metal layer is less than or equal to the height of the second metal layer. The cap layers are respectively disposed in a top surface of the first metal layer and a top surface of the second metal layer.

Abstract translation: 金属栅极结构至少包括衬底，电介质层，第一和第二沟槽，第一金属层和第二金属层以及两个盖层。 特别地，介电层设置在基板上，并且第一和第二沟槽设置在电介质层中。 第一沟槽的宽度小于第二沟槽的宽度。 第一和第二金属层分别设置在第一沟槽和第二沟槽中，第一金属层的高度小于或等于第二金属层的高度。 盖层分别设置在第一金属层的顶表面和第二金属层的顶表面中。