Abstract:
A power-saving method of continuous display and effective cost in a system that includes memory directly accessed by a CPU and at least one display device within vertical blanking. The method includes the following steps: issuing a Power-saving related message; dropping the Power-saving related message, wherein a Power-saving related flag is not set; setting the Power-saving related flag; setting a VID/FID pending bit in the CPU, wherein the vertical blanking of the d display/displays occurs and clearing the Power-saving related flag, wherein the Power-saving related flag is set, and executing a power saving process.
Abstract:
A frequency synchronization apparatus and method for OFDM systems. The frequency synchronization apparatus is comprised of a digital mixer, a first synchronizer and a second synchronizer. The digital mixer acquires a baseband signal by means of a local frequency and adjusts the local frequency in response to an integer frequency offset and a fractional frequency offset. The first synchronizer takes a sequence of received samples derived from the baseband signal in a time domain to estimate the fractional frequency offset. The fractional frequency offset is fed back to the digital mixer. After that, the second synchronizer takes a sequence of demodulated symbols derived from the baseband signal in a frequency domain. The second synchronizer yields the integer frequency offset through a coarse search stage and a fine search stage. Then, the integer frequency offset is fed back to the digital mixer.
Abstract:
A load board for packaged IC testing. The load board with predetermined testing circuit thereon has bonding pad areas on its surface. A plurality of bonding pads is formed on the bonding pad areas, each of which is disposed corresponding to a lead of a packaged IC for testing connection, such as a quad flat packaged IC (QFP), a dual inline packaged IC (DIP) or a small outline packaged IC (SOP). The bonding pads on the load board connect the leads of the testing IC directly during IC testing, thus the conventional test socket between a conventional load board and a packaged IC is omitted.
Abstract:
A method for scaling a digital picture to generate a scaled picture including following steps:(a) scaling a portion of the digital picture instead of the whole digital picture in a first direction; (b) scaling part of the data produced in step (a) in a second direction; and (c) repeating steps (a) and (b) to form the scaled picture.
Abstract:
A method and apparatus for improving bandwidth for depth information communication in a computer graphics system. In operation, a decoder checks a type table associated with a collection of pixels in a memory unit in response to a request for depth information with respect to the collection of pixels. If the type table indicates that the depth information with respect to the collection of pixels has been encoded previously, the decoder computes depth values corresponding to the collection of pixels for each visible polygon in accordance with respective sets of plane parameters in a parameter record associated with a plane pattern, and reconstructs the depth information from the depth values for each visible polygon in accordance with the plane pattern. When the collection of pixels is modified by a new polygon, an encoder updates the plane pattern, the parameter record, and the type table in the memory unit.
Abstract:
A method for a 3:2 pull-down film source detection. First, a source is received. Then, field differences of two fields of the same type in the source and an average field difference according to the field difference corresponding to at least one prior field in the source are calculated. The source is established as a 3:2 pull-down film source by checking whether a 3:2 pull-down signature is in the source according to the field difference and the average field difference, and a bad editing point is detected according to an interlaced frame information of the source.
Abstract:
An apparatus for generating an interleaved stereo image includes a 3D graphics engine, an interleaved data merger and a register. The 3D graphics engine generates a shrunken left-eye image and a shrunken right-eye image of a stereo image based on video source data, the vertical sizes of the shrunken left-eye image and the shrunken right-eye image are shrunk compared with the vertical size of the video source data. The interleaved data merger stores the shrunken left-eye image and the shrunken right-eye image into two consecutive memory segments, and scans the memory segments while displaying the stereo image. A register controls a line number of a display region, so that the rows of the left-eye image shrunk and the right-eye image shrunk arrive at the display region in line-interleaved order. The invention also discloses a method for generating an interleaved stereo image.
Abstract:
A method for detecting dynamic video pixels by using adaptive counter threshold values according to field difference value of the frame in the video, thereby to determine whether the frame is an interlaced frame or a progressive frame and to eliminate incorrect judgements resulting from field difference and to improve accuracy of frame determination.
Abstract:
An apparatus for computing a logarithm to a base p of a floating-point number X. The floating-point number X is represented in the format of (−1)Sx·2Ex·Mx, where Mx=(1+fx)=(1+Ax·2−K)+(Bx·2−N), where Sx is a sign, Ex is an exponent, Mx is a mantissa, 1≦Mx
Abstract translation:一种用于计算浮点数X的基数p的对数的装置。浮点数X以(-1)×S×...×2×Ex× 其中M x x =(1 + f x x)=(1 + A x x) 其中S X是一个符号,其中S x是一个符号, E x是一个指数,M x是尾数,1 <= M×××<2,F 是N位分数,A x S是f x x的最高有效K位的值,B x x是 f(x),0 <= K
Abstract:
The invention provides a semiconductor package substrate, which includes a substrate, a chip contact area, an inner pad portion, an outer pad portion and a conductive layer. The chip contact area, the inner pad portion, the outer pad portion and the conductive layer are formed on one side of the substrate, wherein the outer pad portion encloses the inner pad portion that surrounds the chip contact area in the center of the substrate. The inner pad portion and the outer pad portion contain a plurality of signal pads and a plurality of shielding pads respectively, while the conductive layer and each of the shielding pads are electrically connected.