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    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    32.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20140077392A1

    公开(公告)日：2014-03-20

    申请号：US14085124

    申请日：2013-11-20

    Applicant: FUJITSU SEMICONDUCTOR LIMITED

    Inventor： Kenichi Watanabe

    IPC: H01L23/522

    CPC classification number: H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

    Abstract translation: 半导体器件具有形成在衬底10上的绝缘膜40,42; 埋置在绝缘膜40,42的至少表面侧的互连件58; 绝缘膜60,62形成在绝缘膜42上并且包括孔形通孔60和具有以直角弯曲的图案的槽形通孔66a; 以及埋入孔形通孔60和槽形通孔66a中的埋入导体70,72a。 形成沟槽状的通孔66a的宽度小于孔状通孔66的宽度。可以防止埋入导体的填充不充分和层间绝缘膜的开裂。 导体插头上的步骤可以减少。 因此，可以防止与上部互连层的不良接触以及在形成膜中发生的问题。

    SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE
    34.
    发明申请
    SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE 有权
    半导体器件制造方法和半导体器件

    公开(公告)号：US20130320543A1

    公开(公告)日：2013-12-05

    申请号：US13788894

    申请日：2013-03-07

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Masakatsu TSUCHIAKI

    IPC: H01L21/768 ,  H01L23/532

    CPC classification number: H01L21/76889 ,  H01L21/76885 ,  H01L23/53204 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/148 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device is manufactured by forming, on an insulating base material, a first support element having a side face that extends from a surface of the insulating base material, forming a coating of amorphous silicon on the side face of the first support element, filling an aperture disposed between the first support element and a second support element that extends from a surface of the insulating base material with an insulating film, planarizing the insulating film to expose an exposed portion of the coating and a surface of the first support element, and siliciding the amorphous silicon of the coating to form an interconnect.

    Abstract translation: 半导体器件通过在绝缘基材上形成具有从绝缘基材的表面延伸的侧面的第一支撑元件，在第一支撑元件的侧面上形成非晶硅的涂层，填充 设置在所述第一支撑元件和第二支撑元件之间的孔，所述第二支撑元件由绝缘基材的表面以绝缘膜延伸，平坦化所述绝缘膜以暴露所述涂层的暴露部分和所述第一支撑元件的表面，以及 硅化涂层的非晶硅以形成互连。

    INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME
    37.
    发明申请
    INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME 有权
    互连结构及其制作方法

    公开(公告)号：US20120171862A1

    公开(公告)日：2012-07-05

    申请号：US13415159

    申请日：2012-03-08

    Applicant: Ya Ou ,  Shom Ponoth ,  Terry A. Spooner

    Inventor： Ya Ou ,  Shom Ponoth ,  Terry A. Spooner

    IPC: H01L21/768

    CPC classification number: C23F4/00 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76849 ,  H01L23/5226 ,  H01L23/53204 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An interconnect structure and method of fabricating the same is provided. More specifically, the interconnect structure is a defect free capped interconnect structure. The structure includes a conductive material formed in a trench of a planarized dielectric layer which is devoid of cap material. The structure further includes the cap material formed on the conductive material to prevent migration. The method of forming a structure includes selectively depositing a sacrificial material over a dielectric material and providing a metal capping layer over a conductive layer within a trench of the dielectric material. The method further includes removing the sacrificial material with any unwanted deposited or nucleated metal capping layer thereon.

    Abstract translation: 提供了互连结构及其制造方法。 更具体地，互连结构是无缺陷的封装互连结构。 该结构包括形成在没有帽材料的平坦化介电层的沟槽中的导电材料。 该结构还包括形成在导电材料上以防止迁移的盖材料。 形成结构的方法包括在电介质材料上选择性地沉积牺牲材料，并在介电材料的沟槽内的导电层上提供金属覆盖层。 该方法还包括用其上的任何不需要的沉积或有核的金属覆盖层去除牺牲材料。

    Interconnection structure and method of manufacturing the same, and electronic device including the interconnection structure
    40.
    发明授权
    Interconnection structure and method of manufacturing the same, and electronic device including the interconnection structure 有权

    公开(公告)号：US12027457B2

    公开(公告)日：2024-07-02

    申请号：US17836934

    申请日：2022-06-09

    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

    Inventor： Huilong Zhu

    IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

    CPC classification number: H01L23/5226 ,  H01L21/7682 ,  H01L21/76885 ,  H01L23/53204

    Abstract: An interconnection structure and a method of manufacturing the same, and an electronic device including the interconnection structure are provided. According to an embodiment, the interconnection structure includes: a first interconnection line at a first level, including at least a first portion extending along a first direction; a second interconnection line at a second level higher than the first level, including at least a second portion extending along a second direction crossing the first direction; a via plug disposed between the first portion of the first interconnection line and the second portion of the second interconnection line, and configured to electrically connect the first interconnection line and the second interconnection line, wherein the via plug includes a first pair of sidewalls respectively extending substantially parallel to corresponding sidewalls of the first portion and a second pair of sidewalls respectively extending substantially parallel to corresponding sidewalls of the second portion.

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