公开(公告)号：US11842993B2

公开(公告)日：2023-12-12

申请号：US18064690

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Cheng Tseng ,  Yu-Chih Huang ,  Chih-Hsuan Tai ,  Ting-Ting Kuo ,  Chi-Hui Lai ,  Ban-Li Wu ,  Chiahung Liu ,  Hao-Yi Tsai

IPC: H01L27/01 ,  H01L21/70 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L49/02 ,  H01L25/10

CPC classification number: H01L27/013 ,  H01L21/705 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5286 ,  H01L24/13 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L25/105 ,  H01L2224/13025 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.

公开(公告)号：US20230369204A1

公开(公告)日：2023-11-16

申请号：US17662790

申请日：2022-05-10

Applicant: Infineon Technologies AG

Inventor： Marcus Nuebling ,  Mathias Racki

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/06

CPC classification number: H01L23/5227 ,  H01L23/5225 ,  H01L28/10 ,  H01L27/0629

Abstract: An example circuit includes a coil structure located on at least a first layer of an integrated circuit (IC); and a circuit component comprising conduction paths. The conduction paths are located on one or more layers separate from the first layer and the first layer and the one or more layers form parallel planes. The conduction paths of the circuit component are oriented to avoid eddy currents in the conduction paths caused by an electric current through the coil structure and form a patterned shield. At least some of the conduction paths define an area, and the coil structure is located within the defined area.

公开(公告)号：US20230361156A1

公开(公告)日：2023-11-09

申请号：US18353307

申请日：2023-07-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Cheng CHEN ,  Wei-Li HUANG ,  Chien-Chih KUO ,  Hon-Lin HUANG ,  Chin-Yu KU ,  Chen-Shien CHEN

IPC: H10B61/00 ,  H01L23/00 ,  H01F41/04 ,  H01L23/31 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L28/10 ,  H01L24/05 ,  H01L24/32 ,  H01F41/046 ,  H01L23/3114 ,  H01L23/53204 ,  H01L23/3171 ,  H01L21/76823 ,  H01L24/48 ,  H01L2224/04073 ,  H01L2224/04042 ,  H01L2224/05

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a magnetic element over the substrate. The semiconductor device structure also includes an isolation element partially covering the magnetic element. The semiconductor device structure further includes a conductive feature over the isolation element.

公开(公告)号：US20230352351A1

公开(公告)日：2023-11-02

申请号：US17731145

申请日：2022-04-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： PEI-LUM MA ,  KUN DA JHONG ,  HSUEH-HAN LU ,  KUN-EI CHEN ,  CHEN-CHIEH CHIANG ,  LING-SUNG WANG

IPC: H01L21/66 ,  H01L23/00 ,  H01L49/02

CPC classification number: H01L22/32 ,  H01L24/02 ,  H01L22/12 ,  H01L22/14 ,  H01L24/05 ,  H01L24/03 ,  H01L24/06 ,  H01L28/10 ,  H01L2224/0235 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/0363 ,  H01L2224/0392 ,  H01L2224/0391 ,  H01L2224/05013 ,  H01L2224/05015 ,  H01L2224/05012 ,  H01L2224/06515 ,  H01L2224/0603 ,  H01L2224/05073 ,  H01L2224/05564 ,  H01L2224/05573 ,  H01L2224/05686

Abstract: A semiconductor structure is provided. The semiconductor structure includes an interconnection structure, a first conductive pad, a second conductive pad, a conductive material and a conductive coil. The first and second conductive pads are disposed over and electrically connected to the interconnection structure individually. The conductive material is electrically isolated from the interconnection structure, wherein bottom surfaces of the conductive material, the first conductive pad and the second conductive pad are substantially aligned. The conductive coil is disposed in the interconnection structure and overlapped by the conductive material. A manufacturing method of a semiconductor structure is also provided.

公开(公告)号：US11798978B2

公开(公告)日：2023-10-24

申请号：US17019621

申请日：2020-09-14

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John L. Melanson ,  Lei Zhu ,  Wai-Shun Shum ,  Xiaofan Fei ,  Johann G. Gaboriau

IPC: H01L23/52 ,  H01L49/02 ,  H03F1/02 ,  H01L23/522

CPC classification number: H01L28/10 ,  H01L23/5227 ,  H03F1/0272

Abstract: A single integrated circuit may include a signal path configured to generate an output signal from an input signal, wherein the signal path includes an amplifier configured to drive the output signal, a direct-current-to-direct-current (DC-DC) power converter having a power inductor integrated in the single integrated circuit and configured to generate a supply voltage to the amplifier from a source voltage to the DC-DC power converter, and control circuitry for controlling operation of converter switches of the DC-DC power converter in order that the supply voltage tracks at least one among the input signal and the output signal.

公开(公告)号：US20230335511A1

公开(公告)日：2023-10-19

申请号：US18340366

申请日：2023-06-23

Applicant: Silego Technology Inc.

Inventor： John McDonald ,  Tom Truong ,  David Kunteh Chow

IPC: H01L23/64 ,  H01L23/498

CPC classification number: H01L23/645 ,  H01L23/49838 ,  H01L28/10 ,  H01L23/49894

Abstract: A packaging substrate and a method for mounting an integrated circuit and/or a circuit component is presented. The packaging substrate includes an upper surface for mounting the integrated circuit and/or circuit component; a lower surface opposite to the upper surface, wherein the lower surface is for mounting to a printed circuit board (PCB); a non-conductive material; wherein the non-conductive material is a plastic: an inductor structure at least partially embedded in the non-conductive material; first and second conductive materials, and conductive pillars, arranged to form a first coil and a second coil having an inductance; wherein the first coil and second coil are arranged as a toroid transformer wound in a double helix configuration.

公开(公告)号：US20230307441A1

公开(公告)日：2023-09-28

申请号：US17706454

申请日：2022-03-28

Applicant: Intel Corporation

Inventor： Ahmed ABOU-ALFOTOUH ,  Jonathan DOUGLAS ,  Alan WU ,  Nachiket Venkappayya DESAI ,  Han Wui THEN ,  Harish KRISHNAMURTHY ,  Kaladhar RADHAKRISHNAN ,  Sanka GANESAN ,  Krishnan RAVICHANDRAN

IPC: H01L27/06 ,  H05K1/18 ,  H01F27/28 ,  H01F27/24 ,  H01F27/40 ,  H01L49/02 ,  H01L29/20 ,  H01L29/40 ,  H01L29/778

CPC classification number: H01L27/0605 ,  H05K1/181 ,  H01F27/28 ,  H01F27/24 ,  H01F27/40 ,  H01L28/10 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/7786 ,  H05K2201/1003 ,  H05K2201/10734

Abstract: Embodiments disclosed herein include a coupled inductor. In an embodiment, the coupled inductor comprises a first inductor and a second inductor. In an embodiment, the first inductor can be coupled to the first inductor. In an embodiment, the coupled inductor further comprises a first switch coupled to the first inductor, where the first switch comprises gallium and nitrogen, and a second switch coupled to the second inductor, where the second switch comprises gallium and nitrogen.

公开(公告)号：US11770113B2

公开(公告)日：2023-09-26

申请号：US17561088

申请日：2021-12-23

Applicant: IMEC USA NANOELECTRONICS DESIGN CENTER, Inc.

Inventor： Quentin Paul Herr ,  Anna Yurievna Herr

IPC: H03K17/92 ,  H03H11/02 ,  H01L49/02 ,  H10N60/12 ,  H10N60/80 ,  H10N60/01 ,  H10N69/00

CPC classification number: H03H11/02 ,  H01L28/10 ,  H01L28/60 ,  H03K17/92 ,  H10N60/0912 ,  H10N60/12 ,  H10N60/805 ,  H10N69/00

Abstract: A superconducting circuit comprises a resonator and a Josephson junction. The resonator comprises an inductor and a capacitor. The inductor comprises a first terminal and a second terminal. The second terminal of the inductor is electrically coupled to a first terminal of the capacitor. A second terminal of the capacitor is electrically coupled to a first terminal of the Josephson junction. The terminal shared by the inductor and the capacitor is configured to be electrically coupled to an alternating current (AC) voltage source having a particular frequency and particular phase. The inductance of the inductor and the capacitance of the capacitor are selected to cause the resonator to resonate at a frequency and a phase that substantially match the particular frequency and the particular phase, respectively, of the AC voltage source to facilitate switching a state of the Josephson junction via a single flux quantum (SFQ) pulse.

公开(公告)号：US11756985B2

公开(公告)日：2023-09-12

申请号：US16764585

申请日：2017-11-16

Applicant: Georgia Tech Research Corporation ,  NITTO DENKO CORPORATION

Inventor： Markondeya Raj Pulugurtha ,  Yoshihiro Furukawa ,  Himani Sharma ,  Keiji Takemura ,  Rao R. Tummala ,  Teng Sun

IPC: H01F27/24 ,  H01L49/02 ,  H01F27/245 ,  H01F27/32 ,  H01F27/28

CPC classification number: H01L28/10 ,  H01F27/245 ,  H01F27/324 ,  H01F27/24 ,  H01F27/2871

Abstract: An exemplary embodiment of the present invention provides a planar inductor including a substrate, a first magnetic layer, a conductive coil, and a second magnetic layer. The first magnetic layer can be disposed on at least a portion of the substrate. The conductive coil can be disposed on a first portion of the first magnetic layer. The second magnetic layer can be disposed on a second portion of the first magnetic layer and on at least a portion of the conductive coil.

公开(公告)号：US20230261036A1

公开(公告)日：2023-08-17

申请号：US18139348

申请日：2023-04-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua CHEN ,  Teck-Chong LEE

IPC: H01L27/08 ,  H01L23/522

CPC classification number: H01L28/10 ,  H01L23/5227 ,  H01L23/522 ,  H01L23/5223 ,  H01L23/642

Abstract: A semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface. The first patterned conductive layer is on the top surface of the substrate. The second patterned conductive layer contacts the first patterned conductive layer. The second patterned conductive layer includes a first portion, a second portion and a third portion. The second portion is connected between the first portion and the third portion. The dielectric layer is on the top surface of the substrate. The dielectric layer covers the first patterned conductive layer and surrounds the second portion and the third portion of the second patterned conductive layer. The first portion of the second patterned conductive layer is disposed on the dielectric layer. The third patterned conductive layer is on the second patterned conductive layer, and the connector is directly on the third patterned conductive layer.