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公开(公告)号：US20190278736A1
公开(公告)日：2019-09-12
申请号：US16298373
申请日：2019-03-11
Applicant: Analog Devices Global Unlimited Company
Inventor： David AHERNE , Jofrey SANTILLAN , Wes Vernon LOFAMIA , Paul O'SULLIVAN , Padraig McDAID
IPC: G06F13/42
Abstract: SPI Round Robin Mode for Single-Cycle MUX Channel Sequencing. SPI round robin mode is an SPI mode applicable for MUX devices control. It allows the MUX output to connect to the next input channel sequentially in just one clock cycle. Configurations can be made such as: clock edge to use (rising/falling), ascending/descending channel sequence, and enabling/disabling the channels to go through. The device supersedes an ADC with built in sequencing and is applicable to multiplexing, switching, instrumentation, process control and isolation application—while retaining SPI device control and operation.
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公开(公告)号：US10367516B2
公开(公告)日：2019-07-30
申请号：US15674985
申请日：2017-08-11
Applicant: Analog Devices Global
Inventor： Frederick Carnegie Thompson , Varun Agrawal , Jose Barreiro Silva , Declan M. Dalton
IPC: H03L7/16 , H03M1/08 , H03K5/1252 , H03K7/06 , H03L7/089 , H03M1/06 , H03M1/12 , H04L27/06 , H03M1/74 , H03M3/00
Abstract: This disclosure relates to data converters for electronic systems. An example system includes a primary analog to digital converter (ADC) circuit, a slope calculation circuit, a digital phase lock loop (DPLL) circuit, a sampling error circuit, and a summing circuit. The primary ADC circuit samples an input signal and produces a digital output signal representative of the input signal. The slope calculation circuit generates a digital slope signal representative of slope of the input signal, and the DPLL circuit provides a sampling clock signal to the primary ADC circuit. The sampling error circuit generates a sampling error signal representative of sampling error by the primary ADC circuit using the digital slope signal and the sampling clock signal. The summing circuit receives the sampling error signal and the digital output signal of the primary ADC circuit and generates an adjusted digital output signal representative of the input signal.
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公开(公告)号：US10367411B2
公开(公告)日：2019-07-30
申请号：US15849047
申请日：2017-12-20
Applicant: Analog Devices Global Unlimited Company
Inventor： Francis Martin
Abstract: A power factor correction device for providing tolerance to a fault condition in an input supply can include a first boost circuit, a second boost circuit, and a controller circuit. The controller circuit can interleave operation of the first boost circuit and operation of the second boost circuit such as to generate an output voltage when the input supply is received at the power factor correction device. The controller circuit can route, in response to the fault condition, a stored supply of the second boost circuit to an input of the first boost circuit. The controller circuit can control the first boost circuit to maintain the output voltage.
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公开(公告)号：US10365322B2
公开(公告)日：2019-07-30
申请号：US15490584
申请日：2017-04-18
Applicant: Analog Devices Global
Inventor： Edward John Coyne , Alan J. O'Donnell , Shaun Bradley , David Aherne , David Boland , Thomas G. O'Dwyer , Colm Patrick Heffernan , Kevin B. Manning , Mark Forde , David J. Clarke , Michael A. Looby
IPC: G01R31/28
Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.
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45.发明授权公开(公告)号：US10348250B2
公开(公告)日：2019-07-09
申请号：US15790793
申请日：2017-10-23
Applicant: Analog Devices Global Unlimited Company
Inventor： Dennis A. Dempsey
Abstract: The noise power of an amplifier or buffer can increase towards the unity gain crossover frequency of the amplifier. The inventor realized that many applications do not require the full bandwidth capability of the amplifier all of the time and hence step could be taken to reduce the bandwidth at the output of the amplifier and hence the noise power can be reduced when appropriate, taking other operating requirements into consideration.
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Patent Agency Ranking
公开(公告)号：US10346273B2
公开(公告)日：2019-07-09
申请号：US15713090
申请日：2017-09-22
Applicant: Analog Devices Global Unlimited Company
Inventor： Courtney E. Fricano , Paul P. Wright , David Brownell
IPC: G06F11/22 , G01R31/28 , G01R31/3183 , G06F17/50
Abstract: Systems and methods are provided for an automated analog fault injection including creating a list of fault models for injection to an analog circuit, adding a first fault placeholder to the analog circuit, running fault simulations by replacing the first fault placeholder with a first fault model from the list of fault models, and determining whether the first fault model is detected.
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公开(公告)号：US10340700B2
公开(公告)日：2019-07-02
申请号：US15224071
申请日：2016-07-29
Applicant: Analog Devices Global
Inventor： Junifer Frenila , Perryl Glo Angac , Oliver Silvela, Jr.
Abstract: According to some aspects, a power regulation system for energy harvesters that lacks a battery is provided. In some embodiments, the power regulation system may receive power from multiple energy harvesters that generate energy from different sources, such as wind currents and ambient light. In these embodiments, the power regulation system may selectively provide power from one or more of the energy harvesters to a load as environmental conditions change and power itself with energy from the energy harvesters. Thereby, the power regulation system may start and operate without a battery and provide power to the load over a wider range of environmental conditions.
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公开(公告)号：US10310476B2
公开(公告)日：2019-06-04
申请号：US15958871
申请日：2018-04-20
Applicant: Analog Devices Global Unlimited Company
Inventor： Navdeep Singh Dhanjal , Shengbing Zhou
IPC: H03K19/173 , G05B19/045 , G06F1/3296 , H03K19/00 , G06F12/0817
Abstract: An apparatus comprises an integrated circuit (IC) including sequencer circuitry; and a memory integral to or operatively coupled to the integrated circuit, wherein at least a portion of the memory is organized as a plurality of hierarchical linked lists defining a finite state machine of a plurality of finite IC states; wherein the sequencer circuitry is configured to: receive one or more control words from the hierarchical linked lists associated with an IC state; advance the IC to the IC state according to the one or more control words; and perform one or more actions corresponding to the IC state.
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公开(公告)号：US20190140656A1
公开(公告)日：2019-05-09
申请号：US15895661
申请日：2018-02-13
Applicant: Analog Devices Global Unlimited Company
Inventor： Fergus John Downey
IPC: H03M1/78
Abstract: Digital to analog converter architectures are disclosed that enable the binary scaling of transistor sized to be replaced by transistors of substantially the same size. This significantly reduced the size of the Digital to Analog converter on a wafer. As the currents from the lesser bits of the converter may be very small indeed, some of the transistors are operated in a regime where the gate-source voltage applied to the transistor is below the threshold voltage for the device, the threshold voltage generally being regarded as marking the onset of significant conduction through a field effect transistor.
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公开(公告)号：US10277433B1
公开(公告)日：2019-04-30
申请号：US15813905
申请日：2017-11-15
Applicant: Analog Devices Global Unlimited Company
Inventor： Jacobo Riesco-Prieto , Philip Curran , Michael McCarthy
Abstract: This disclosure relates to data communication networks. An example data communication apparatus includes physical (PHY) layer circuitry that includes transceiver circuitry, decoder circuitry, and a signal analysis unit. The transceiver circuitry receives encoded data symbols via a network link. The received encoded data symbols are encoded using trellis coded modulation (TCM). The decoder circuitry decodes the received encoded data symbols using maximum-likelihood (ML) decoding to map a received symbol sequence to an allowed symbol sequence using a trace-back depth. A trace-back depth value is a number of symbols in the received symbol sequence used by the ML decoding to identify the allowed symbol sequence from the received symbol sequence. The signal analysis unit determines one or more link statistics of the network link, and sets the trace-back depth value according to the one or more link statistics.
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