公开(公告)号：US20110134137A1

公开(公告)日：2011-06-09

申请号：US12633062

申请日：2009-12-08

Applicant: Victor W. Lee ,  Mikhail Smelyanskiy ,  Ganesh S. Dasika ,  Jose Gonzalez ,  Jatin Chhugani ,  Yen-Kuang Chen ,  Changkyu Kim ,  Julio Gago ,  Santiago Galan ,  Victor Moya Del Barrio

Inventor： Victor W. Lee ,  Mikhail Smelyanskiy ,  Ganesh S. Dasika ,  Jose Gonzalez ,  Jatin Chhugani ,  Yen-Kuang Chen ,  Changkyu Kim ,  Julio Gago ,  Santiago Galan ,  Victor Moya Del Barrio

IPC: G09G5/00

CPC classification number: G06T11/001 ,  G06F17/16 ,  G06T1/00

Abstract: A texture unit may be used utilized to perform general purpose mathematical computations such as dot products. This enables some general purpose computations and operations to be offloaded from a central processing unit to the texture unit. The texture unit may use linear interpolators in order to perform the dot product calculations.

Abstract translation: 可以使用纹理单元来执行诸如点积的通用数学计算。 这使得一些通用计算和操作能够从中央处理单元卸载到纹理单元。 纹理单元可以使用线性内插器来执行点积计算。

公开(公告)号：US20090013160A1

公开(公告)日：2009-01-08

申请号：US12166439

申请日：2008-07-02

Applicant: Douglas C. Burger ,  Stephen W. Keckler ,  Robert McDonald ,  Paul Gratz ,  Nitya Ranganathan ,  Lakshminarasimhan Sethumadhavan ,  Karthikevan Sankaralingam ,  Ramadass Nagarajan ,  Changkyu Kim ,  Haiming Liu

Inventor： Douglas C. Burger ,  Stephen W. Keckler ,  Robert McDonald ,  Paul Gratz ,  Nitya Ranganathan ,  Lakshminarasimhan Sethumadhavan ,  Karthikevan Sankaralingam ,  Ramadass Nagarajan ,  Changkyu Kim ,  Haiming Liu

IPC: G06F9/00 ,  G06F12/00

CPC classification number: G06F9/3885 ,  G06F9/3836 ,  G06F9/3897 ,  G06F12/0875 ,  G06F15/7867 ,  Y02D10/12 ,  Y02D10/13

Abstract: A method, system and computer program product for dynamically composing processor cores to form logical processors. Processor cores are composable in that the processor cores are dynamically allocated to form a logical processor to handle a change in the operating status. Once a change in the operating status is detected, a mechanism may be triggered to recompose one or more processor cores into a logical processor to handle the change in the operating status. An analysis may be performed as to how one or more processor cores should be recomposed to handle the change in the operating status. After the analysis, the one or more processor cores are recomposed into the logical processor to handle the change in the operating status. By dynamically allocating the processor cores to handle the change in the operating status, performance and power efficiency is improved.

Abstract translation: 一种用于动态组成处理器内核以形成逻辑处理器的方法，系统和计算机程序产品。 处理器核心是可组合的，因为处理器核心被动态地分配以形成逻辑处理器来处理操作状态的改变。 一旦检测到操作状态的改变，则可以触发一种机制来将一个或多个处理器核重组到逻辑处理器中以处理操作状态的变化。 可以执行关于如何重组一个或多个处理器核来处理操作状态的变化的分析。 在分析之后，将一个或多个处理器核重新组合到逻辑处理器中以处理操作状态的改变。 通过动态分配处理器核来处理运行状态的变化，提高了性能和功率效率。

公开(公告)号：US06965969B2

公开(公告)日：2005-11-15

申请号：US10962295

申请日：2004-10-08

Applicant: Doug Burger ,  Stephen W. Keckler ,  Changkyu Kim

Inventor： Doug Burger ,  Stephen W. Keckler ,  Changkyu Kim

IPC: G06F12/00 ,  G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0897 ,  G06F12/0846 ,  G06F12/12 ,  G06F2212/271

Abstract: An apparatus or system may comprises cache control circuitry coupled to a processor, and a plurality of independently accessible memory banks (228) coupled to the cache control circuitry. Some of the banks may have non-uniform latencies, organized into two or more spread bank sets (246). A method may include accessing data in the banks, wherein selected banks are closer to the cache control circuitry and/or processor than others, and migrating a first datum (445) to a closer bank from a further bank upon determining that the first datum is accessed more frequently than a second datum, which may be migrated to the further bank (451).

Abstract translation: 装置或系统可以包括耦合到处理器的高速缓存控制电路和耦合到高速缓存控制电路的多个可独立存取的存储体（228）。 一些银行可能会有不一致的延迟，组织成两个或更多的传播银行集（246）。 方法可以包括访问存储体中的数据，其中所选择的存储体比其他存储体更靠近高速缓存控制电路和/或处理器，并且在确定第一数据是第一数据是第一数据时，将第一数据（445）从另一个存储体迁移到更靠近的存储体 比第二基准更频繁地访问，第二基准可以迁移到另外的银行（451）。