公开(公告)号：US20070238200A1

公开(公告)日：2007-10-11

申请号：US11556489

申请日：2006-11-03

Applicant: Chia-Lin Chen ,  Y. M. Lin ,  Ming-Chen Chen

Inventor： Chia-Lin Chen ,  Y. M. Lin ,  Ming-Chen Chen

IPC: H01L21/00

CPC classification number: G01R31/2642 ,  G01R31/2858 ,  G01R31/3008

Abstract: A method includes measuring a gate leakage current of a plurality of transistors. A single stress bias voltage is applied to the plurality of transistors. The stress bias voltage causes a 10% degradation in a drive current of each transistor within a respective stress period t. One or more relationships are determined, between the measured gate leakage current and one or more of the group consisting of gate voltage, gate length, gate temperature, and gate width of the plurality of transistors, respectively. A negative bias temperature instability (NBTI) lifetime τ of the plurality of transistors is estimated, based on the measured gate leakage current and the one or more relationships.

Abstract translation: 一种方法包括测量多个晶体管的栅极漏电流。 单个应力偏置电压被施加到多个晶体管。 应力偏置电压在相应的应力周期t内导致每个晶体管的驱动电流10％的劣化。 在测量的栅极漏电流和分别由多个晶体管的栅极电压，栅极长度，栅极温度和栅极宽度的组中的一个或多个之间确定一个或多个关系。 基于所测量的栅极泄漏电流和一个或多个关系，估计多个晶体管的负偏压温度不稳定性（NBTI）寿命ττ。

公开(公告)号：US07259050B2

公开(公告)日：2007-08-21

申请号：US10834474

申请日：2004-04-29

Applicant: Chien-Hao Chen ,  Chia-Lin Chen ,  Tze Liang Lee ,  Shih-Chang Chen ,  Ju-Wang Hsu

Inventor： Chien-Hao Chen ,  Chia-Lin Chen ,  Tze Liang Lee ,  Shih-Chang Chen ,  Ju-Wang Hsu

IPC: H01L21/338

CPC classification number: H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843

Abstract: A semiconductor device comprises a substrate, a gate disposed on the substrate, and a source and drain formed in the substrate on both sides of the gate. The device further comprises a thin spacer having a first layer and a second layer formed on the sidewalls of the gate, wherein the first and second layers have comparable wet etch rates of at least 10 Å per minute using the same etchant.

Abstract translation: 半导体器件包括衬底，设置在衬底上的栅极和形成在栅极两侧的衬底中的源极和漏极。 该器件还包括具有形成在栅极的侧壁上的第一层和第二层的薄间隔物，其中使用相同的蚀刻剂，第一层和第二层具有至少每分钟至少10埃的湿蚀刻速率。

公开(公告)号：US07176138B2

公开(公告)日：2007-02-13

申请号：US10970090

申请日：2004-10-21

Applicant: Chien-Hao Chen ,  Vincent S. Chang ,  Ji-Yi Yang ,  Chia-Lin Chen ,  Tze-Liang Lee

Inventor： Chien-Hao Chen ,  Vincent S. Chang ,  Ji-Yi Yang ,  Chia-Lin Chen ,  Tze-Liang Lee

IPC: H01L21/311

CPC classification number: H01L21/76232

Abstract: A method for forming a divot free nitride lined shallow trench isolation (STI) feature including providing a substrate including an STI trench extending through an uppermost hardmask layer into a thickness of the substrate exposing the substrate portions; selectively forming a first insulating layer lining the STI trench over said exposed substrate portions only; backfilling the STI trench with a second insulating layer; planarizing the second insulating layer; and, carrying out a wet etching process to remove the uppermost hardmask layer.

Abstract translation: 一种用于形成无自由度的氮化物衬底浅沟槽隔离（STI）特征的方法，包括提供包括延伸穿过最上面的硬掩模层的STI沟槽的衬底，暴露衬底部分的衬底的厚度; 仅在所述暴露的衬底部分上选择性地形成衬在STI沟槽上的第一绝缘层; 用第二绝缘层回填STI沟槽; 平面化第二绝缘层; 并进行湿蚀刻处理以去除最上面的硬掩模层。

公开(公告)号：US20060099771A1

公开(公告)日：2006-05-11

申请号：US10970090

申请日：2004-10-21

Applicant: Chien-Hao Chen ,  Vincent Chang ,  Ji-Yi Yang ,  Chia-Lin Chen ,  Tze-Liang Lee

Inventor： Chien-Hao Chen ,  Vincent Chang ,  Ji-Yi Yang ,  Chia-Lin Chen ,  Tze-Liang Lee

IPC: H01L21/76

CPC classification number: H01L21/76232

Abstract: A method for forming a divot free nitride lined shallow trench isolation (STI) feature including providing a substrate including an STI trench extending through an uppermost hardmask layer into a thickness of the substrate exposing the substrate portions; selectively forming a first insulating layer lining the STI trench over said exposed substrate portions only; backfilling the STI trench with a second insulating layer; planarizing the second insulating layer; and, carrying out a wet etching process to remove the uppermost hardmask layer.

Abstract translation: 一种用于形成无自由度的氮化物衬底浅沟槽隔离（STI）特征的方法，包括提供包括延伸穿过最上面的硬掩模层的STI沟槽的衬底，暴露衬底部分的衬底的厚度; 仅在所述暴露的衬底部分上选择性地形成衬在STI沟槽上的第一绝缘层; 用第二绝缘层回填STI槽; 平面化第二绝缘层; 并进行湿蚀刻处理以去除最上面的硬掩模层。

公开(公告)号：US20060094194A1

公开(公告)日：2006-05-04

申请号：US10982115

申请日：2004-11-04

Applicant: Chien-Hao Chen ,  Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

Inventor： Chien-Hao Chen ,  Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC: H01L21/336

CPC classification number: H01L21/26513 ,  H01L21/26506 ,  H01L21/2658 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

Abstract: A method of forming a semiconductor device comprises providing a gate electrode having exposed side walls formed in a substrate, forming dummy spacers on the gate electrode exposed side walls, performing a first implant to form source and drain implants, forming a capping layer over the gate electrode, the dummy sidewall spacers, and the source and drain, performing a first anneal, and removing the capping layer and the dummy sidewall spacers.

Abstract translation: 一种形成半导体器件的方法包括提供栅电极，其具有形成在衬底中的暴露的侧壁，在栅极电极暴露的侧壁上形成虚设间隔物，执行第一注入以形成源极和漏极注入，在栅极上形成覆盖层 电极，虚拟侧壁间隔物以及源极和漏极，执行第一退火，以及去除覆盖层和虚设侧壁间隔物。

公开(公告)号：US06933157B2

公开(公告)日：2005-08-23

申请号：US10712460

申请日：2003-11-13

Applicant: Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

Inventor： Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/44

CPC classification number: H01L21/02052 ,  Y10S438/906

Abstract: A method of manufacturing a semiconductor wafer including cleaning a surface of the wafer during a first time period and forming a layer over the surface during a second time period. The first time period includes a cleaning delay period prior to a cleaning portion of the first time period, the cleaning delay period configured such that an end time of the first time period substantially coincides with a start time of the second time period.

Abstract translation: 一种制造半导体晶片的方法，包括在第一时间段期间清洁所述晶片的表面，并且在第二时间段期间在所述表面上形成层。 第一时间段包括在第一时间段的清洁部分之前的清洁延迟时间，清洁延迟时间被配置为使得第一时间段的结束时间基本上与第二时间段的开始时间一致。

公开(公告)号：US20050136583A1

公开(公告)日：2005-06-23

申请号：US10744746

申请日：2003-12-23

Applicant: Chien-Hao Chen ,  Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

Inventor： Chien-Hao Chen ,  Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC: H01L21/8238 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L29/7842 ,  H01L21/823807 ,  H01L21/823842

Abstract: A method of improving CMOS device performance, comprising the following steps. A structure having a gate electrode formed thereover and a channel formed thereunder is provided. The gate electrode having an initial lower width and an initial upper width. A capping layer having a tensile stress is formed over the structure and the gate electrode. The gate electrode is annealed to achieve tensile stress in the channel.

Abstract translation: 一种提高CMOS器件性能的方法，包括以下步骤。 提供了具有形成在其上的栅电极和在其下形成的沟道的结构。 栅电极具有初始下宽度和初始上宽度。 在结构和栅电极上形成具有拉伸应力的覆盖层。 栅电极退火以在通道中实现拉伸应力。

公开(公告)号：US20050056900A1

公开(公告)日：2005-03-17

申请号：US10662845

申请日：2003-09-15

Applicant: Ming-Fang Wang ,  Chia-Lin Chen ,  Chih-Wei Yang ,  Chi-Chun Chen ,  Tuo-Hung Hou ,  Yeou-Ming Lin ,  Liang-Gi Yao ,  Shih-Chang Chen

Inventor： Ming-Fang Wang ,  Chia-Lin Chen ,  Chih-Wei Yang ,  Chi-Chun Chen ,  Tuo-Hung Hou ,  Yeou-Ming Lin ,  Liang-Gi Yao ,  Shih-Chang Chen

IPC: H01L21/28 ,  H01L21/314 ,  H01L29/51 ,  H01L29/76

CPC classification number: H01L29/517 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/3141 ,  H01L29/513

Abstract: A method for forming an improved gate stack structure having improved electrical properties in a gate structure forming process A method for forming a high dielectric constant gate structure including providing a silicon substrate comprising exposed surface portions; forming an interfacial layer over the exposed surface portions having a thickness of less than about 10 Angstroms; forming a high dielectric constant metal oxide layer over the interfacial layer having a dielectric constant of greater than about 10; forming a barrier layer over the high dielectric constant metal oxide layer; forming an electrode layer over the barrier layer; and, etching according to an etching pattern through a thickness of the electrode layer, barrier layer, high dielectric constant material layer, and the interfacial layer to form a high dielectric constant gate structure.

Abstract translation: 一种用于形成在栅极结构形成工艺中具有改进的电性能的改进的栅极堆叠结构的方法用于形成高介电常数栅极结构的方法，包括提供包括暴露表面部分的硅衬底; 在暴露的表面部分上形成具有小于约10埃的厚度的界面层; 在介电常数大于约10的界面层上形成高介电常数金属氧化物层; 在高介电常数金属氧化物层上形成阻挡层; 在阻挡层上形成电极层; 并且根据蚀刻图案通过电极层，阻挡层，高介电常数材料层和界面层的厚度进行蚀刻，以形成高介电常数栅极结构。

公开(公告)号：US06759302B1

公开(公告)日：2004-07-06

申请号：US10209433

申请日：2002-07-30

Applicant: Chia-Lin Chen ,  Chien-Hao Chen ,  Mo-Chiun Yu

Inventor： Chia-Lin Chen ,  Chien-Hao Chen ,  Mo-Chiun Yu

IPC: H01L31119

CPC classification number: H01L21/823857 ,  H01L21/28202 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823878 ,  Y10S438/981

Abstract: A method of forming multiple gate oxide thicknesses on active areas that are separated by STI isolation regions on a substrate. A first layer of oxide is grown to a thickness of about 50 Angstroms and selected regions are then removed. A second layer of oxide is grown that is thinner than first growth oxide. For three different gate oxide thicknesses, selected second oxide growth regions are nitridated with a N2 plasma which increases the dielectric constant of a gate oxide and reduces the effective oxide thickness. To achieve four different gate oxide thicknesses, nitridation is performed on selected first growth oxides and on selected second growth oxide regions. Nitridation of gate oxides also prevents impurity dopants from migrating across the gate oxide layer and reduces leakage of standby current. The method also reduces corner loss of STI regions caused by HF etchant.

公开(公告)号：US20170190031A1

公开(公告)日：2017-07-06

申请号：US15356634

申请日：2016-11-20

Applicant: Chia-Lin Chen

Inventor： Chia-Lin Chen

IPC: B25B23/12 ,  B25B23/00 ,  B25B13/06

CPC classification number: B25B23/12 ,  B25B13/06 ,  B25B23/0057

Abstract: A magnetic socket contains: a body and at least one magnetic attraction element. The body includes a connection segment and a fitting section, the connection segment has a polygonal coupling orifice defined therein and configured to accommodate a socket wrench, and the fitting section has a locking orifice formed therein and configured to lock a screw or a nut made of metal, wherein the locking orifice is polygonal. The body further includes at least one through orifice arranged on the fitting section and communicating with the locking orifice, and each of the at least one magnetic attraction element is housed in each of the at least one through orifice. Thereby, the magnetic socket is driven by the socket wrench so as to rotatably lock or remove a screw or a nut, and the magnetic socket magnetically attracts the screw or the nut, after removing the screw or the nut.