公开(公告)号：US20130049138A1

公开(公告)日：2013-02-28

申请号：US13634266

申请日：2011-11-18

Applicant: Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

Inventor： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

IPC: H01L29/78 ,  H01L21/28

CPC classification number: H01L21/823431

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: a semiconductor layer; a first fin being formed by patterning the semiconductor layer; and a second fin being formed by patterning the semiconductor layer, wherein: top sides of the first and second fins have the same height; bottom sides of the first and second fins adjoin the semiconductor layer; and the second fin is higher than the first fin. According to the present disclosure, a plurality of semiconductor devices with different dimensions can be integrated on the same wafer. As a result, manufacturing process can be shortened and manufacturing cost can be reduced. Furthermore, devices with different driving capabilities can be provided.

Abstract translation: 本发明提供一种半导体器件及其制造方法。 半导体器件包括：半导体层; 通过图案化半导体层形成第一鳍片; 并且通过图案化半导体层形成第二鳍片，其中：第一鳍片和第二鳍片的顶侧具有相同的高度; 第一和第二散热片的底面邻接半导体层; 第二鳍高于第一鳍。 根据本公开，可以将多个具有不同尺寸的半导体器件集成在同一晶片上。 结果，可以缩短制造工序，降低制造成本。 此外，可以提供具有不同驱动能力的装置。

公开(公告)号：US20130049125A1

公开(公告)日：2013-02-28

申请号：US13375692

申请日：2011-08-29

Applicant: Huicai Zhong ,  Jun Luo ,  Qingqing Liang ,  Huilong Zhu

Inventor： Huicai Zhong ,  Jun Luo ,  Qingqing Liang ,  Huilong Zhu

IPC: H01L27/088 ,  H01L21/283

CPC classification number: H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L27/1211

Abstract: A semiconductor device structure and a method for manufacturing the same are disclosed. In one embodiment, the method comprises: forming a fin in a first direction on a semiconductor substrate; forming a gate line in a second direction crossing the first direction on the semiconductor substrate, the gate line intersecting the fin via a gate dielectric layer; forming a dielectric spacer surrounding the gate line; forming a conductive spacer surrounding the dielectric spacer; and performing inter-device electrical isolation at a predetermined region, wherein isolated portions of the gate line form gate electrodes of respective unit devices, and isolated portions of the conductive spacer form contacts of the respective unit devices.

Abstract translation: 公开了一种半导体器件结构及其制造方法。 在一个实施例中，该方法包括：在半导体衬底上沿第一方向形成翅片; 在半导体衬底上与第一方向交叉的第二方向上形成栅极线，栅极线经由栅极电介质层与鳍状物相交; 形成围绕所述栅极线的介电隔离层; 形成围绕所述电介质间隔物的导电间隔物; 以及在预定区域执行器件间电隔离，其中栅极线的隔离部分形成各个单元器件的栅电极，并且导电间隔物的隔离部分形成各个单元器件的接触。

公开(公告)号：US20130049092A1

公开(公告)日：2013-02-28

申请号：US13501518

申请日：2011-11-18

Applicant: Qingqing Liang ,  Miao Xu ,  Huilong Zhu ,  Huicai Zhong

Inventor： Qingqing Liang ,  Miao Xu ,  Huilong Zhu ,  Huicai Zhong

IPC: H01L29/786 ,  H01L29/78

CPC classification number: H01L29/78654 ,  H01L29/4908 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78696

Abstract: The present application discloses a semiconductor device comprising a source region and a drain region in an ultra-thin semiconductor layer; a channel region between the source region and the drain region in the ultra-thin semiconductor layer; a front gate stack above the channel region, the front gate comprising a front gate and a front gate dielectric between the front gate and the channel region; and a back gate stack below the channel region, the back gate stack comprising a back gate and a back gate dielectric between the back gate and the channel region, wherein the front gate is made of a high-Vt material, and the back gate is made of a low-Vt material. According to another embodiment, the front gate and the back gate are made of the same material, and the back gate is applied with a forward bias voltage during operation. The semiconductor device alleviates threshold voltage fluctuation due to varied thickness of the channel region by means of the back gate.

Abstract translation: 本申请公开了一种包括超薄半导体层中的源极区域和漏极区域的半导体器件; 在超薄半导体层中的源极区域和漏极区域之间的沟道区域; 在所述沟道区域上方的前栅极堆叠，所述前栅极包括在所述前栅极和所述沟道区域之间的前栅极和前栅极电介质; 以及在沟道区域下方的背栅极堆叠，所述背栅叠层包括在所述背栅极和所述沟道区域之间的背栅极和背栅电介质，其中所述前栅极由高Vt材料制成，并且所述背栅极 由低Vt材料制成。 根据另一实施例，前栅极和后栅极由相同的材料制成，并且背栅在工作期间被施加正偏压。 半导体器件通过后栅极减小由沟道区域的厚度变化引起的阈值电压波动。

公开(公告)号：US20130032777A1

公开(公告)日：2013-02-07

申请号：US13376237

申请日：2011-08-05

Applicant: Haizhou Yin ,  Zhijiong Luo ,  Huilong Zhu

Inventor： Haizhou Yin ,  Zhijiong Luo ,  Huilong Zhu

IPC: H01L29/06 ,  H01L21/20 ,  B82Y99/00 ,  B82Y40/00

CPC classification number: H01L29/45 ,  B82Y10/00 ,  H01L29/1606 ,  H01L29/42316 ,  H01L29/66431 ,  H01L29/7781 ,  H01L29/78618 ,  H01L29/78684 ,  H01L51/0048 ,  H01L51/0562

Abstract: The present invention discloses a semiconductor device and a manufacturing method thereof. The method comprises the steps of providing a substrate on which a graphene layer or carbon nanotube layer is formed; exposing part of the graphene layer or carbon nanotube layer after forming a gate structure on the graphene layer or carbon nanotube layer, wherein the gate structure comprises a gate stack, a spacer and a cap layer, the cap layer is located on the gate stack, and the spacer surrounds the gate stack and the cap layer; epitaxially growing a semiconductor layer on the exposed graphene layer or carbon nanotube layer; and forming a metal contact layer on the semiconductor layer. In the present invention, the semiconductor layer is formed on the graphene layer or carbon nanotube layer, and then the metal contact layer is formed on the semiconductor layer, instead of forming the metal contact layer directly from the graphene layer or carbon nanotube layer. This facilitates to form the self-aligned source and drain contact plugs.

Abstract translation: 本发明公开了一种半导体器件及其制造方法。 该方法包括提供其上形成有石墨烯层或碳纳米管层的基板的步骤; 在石墨烯层或碳纳米管层上形成栅极结构之后暴露部分石墨烯层或碳纳米管层，其中栅极结构包括栅极堆叠，间隔物和覆盖层，盖层位于栅极叠层上， 并且所述间隔件围绕所述栅极堆叠和所述盖层; 在暴露的石墨烯层或碳纳米管层上外延生长半导体层; 以及在所述半导体层上形成金属接触层。 在本发明中，在石墨烯层或碳纳米管层上形成半导体层，然后在半导体层上形成金属接触层，而不是直接从石墨烯层或碳纳米管层形成金属接触层。 这有助于形成自对准的源极和漏极接触插头。

公开(公告)号：US08361875B2

公开(公告)日：2013-01-29

申请号：US12701672

申请日：2010-02-08

Applicant: Huilong Zhu

Inventor： Huilong Zhu

IPC: H01L21/20

CPC classification number: H01L27/10805 ,  H01L27/1085 ,  H01L29/945

Abstract: A pair of through substrate vias is formed through a stack including a lightly doped semiconductor and a bottom semiconductor layer in a semiconductor substrate. The top semiconductor layer includes semiconductor devices such as field effect transistors. At least one deep trench is formed on the backside of the semiconductor substrate in the bottom semiconductor layer and at least one dielectric layer thereupon. A node dielectric and a conductive inner electrode are formed in each of the at least one deep trench. Substrate contact vias abutting the bottom semiconductor layer are also formed in the at least one dielectric layer. Conductive wiring structures on the backside of the semiconductor substrate provide lateral connection between the through substrate vias and the at least one conductive inner electrode and the substrate contact vias.

Abstract translation: 通过在半导体衬底中包括轻掺杂半导体和底部半导体层的堆叠形成一对直通衬底通孔。 顶部半导体层包括诸如场效应晶体管的半导体器件。 至少一个深沟槽形成在半导体衬底的底部半导体层的背面和至少一个电介质层上。 在所述至少一个深沟槽的每一个中形成节点电介质和导电内电极。 邻接底部半导体层的衬底接触通孔也形成在至少一个电介质层中。 在半导体衬底的背面上的导电布线结构提供贯穿衬底通孔与至少一个导电内部电极和衬底接触通孔之间的横向连接。

公开(公告)号：US20130020578A1

公开(公告)日：2013-01-24

申请号：US13521998

申请日：2011-11-30

Applicant: Qingqing Liang ,  Huilong Zhu ,  Huicai Zhong

Inventor： Qingqing Liang ,  Huilong Zhu ,  Huicai Zhong

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856

Abstract: The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention may comprise: an active fin region which is arranged on an insulating layer; a threshold voltage adjusting layer arranged on top of the active fin region, which threshold voltage adjusting layer is used to adjust the threshold voltage of the semiconductor device; a gate stack which is arranged on the threshold voltage adjusting layer, on the sidewalls of the active fin region and on the insulating layer, and comprises a gate dielectric and a gate electrode formed on the gate dielectric; and a source region and a drain region formed in the active fin region on both sides of the gate stack respectively. The semiconductor device according to the invention comprises the threshold voltage adjusting layer which may adjust the threshold voltage of the semiconductor device. This provides a simple and convenient way capable of adjusting the threshold voltage of a semiconductor device comprising an active fin region.

Abstract translation: 本发明涉及半导体器件及其制造方法。 根据本发明的实施例的半导体器件可以包括：布置在绝缘层上的有源鳍片区域; 设置在有源鳍片区域顶部的阈值电压调整层，该阈值电压调整层用于调整半导体器件的阈值电压; 栅极堆叠，其布置在阈值电压调节层上，在有源鳍片区域的侧壁和绝缘层上，并且包括形成在栅极电介质上的栅极电介质和栅电极; 以及分别形成在栅极堆叠两侧的有源鳍片区域中的源极区域和漏极区域。 根据本发明的半导体器件包括可调节半导体器件的阈值电压的阈值电压调节层。 这提供了能够调整包括有源鳍片区域的半导体器件的阈值电压的简单且方便的方式。

公开(公告)号：US20130015497A1

公开(公告)日：2013-01-17

申请号：US13119074

申请日：2011-02-18

Applicant: Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

Inventor： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L29/0847 ,  H01L21/76805 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/78

Abstract: An S/D region including a first region and a second region is provided. The first region is located, with at least a partial thickness, in the substrate. The second region is formed on the first region and made of a material different from that of the first region. A method for forming an S/D region is further provided, and the method includes: forming trenches at both sides of a gate stack structure in a substrate; forming a first semiconductor layer, wherein at least a part of the first semiconductor layer is filled into the trenches; and forming a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer is made of a material different from that of the first semiconductor layer. A contact hole and a forming method thereof are also provided which may increase the contact area between a contact hole and a contact region, and reduce the contact resistance.

Abstract translation: 提供包括第一区域和第二区域的S / D区域。 第一区域在衬底中具有至少部分厚度。 第二区域形成在第一区域上并且由与第一区域不同的材料制成。 还提供了形成S / D区域的方法，该方法包括：在基板中的栅叠层结构的两侧形成沟槽; 形成第一半导体层，其中所述第一半导体层的至少一部分被填充到所述沟槽中; 以及在所述第一半导体层上形成第二半导体层，其中所述第二半导体层由与所述第一半导体层不同的材料制成。 还提供接触孔及其形成方法，其可以增加接触孔和接触区域之间的接触面积，并降低接触电阻。

公开(公告)号：US20130011981A1

公开(公告)日：2013-01-10

申请号：US13614476

申请日：2012-09-13

Applicant: Huilong Zhu ,  Jing Wang

Inventor： Huilong Zhu ,  Jing Wang

IPC: H01L21/336

CPC classification number: H01L21/26586 ,  H01L29/66651 ,  H01L29/7833

Abstract: A semiconductor structure which exhibits high device performance and improved short channel effects is provided. In particular, a metal oxide semiconductor field effect transistor (MOFET) is provided that includes a low dopant concentration within an inversion layer of the structure; the inversion layer is an epitaxial semiconductor layer that is formed atop a portion of the semiconductor substrate. The structure also includes a well region of a first conductivity type beneath the inversion layer, wherein the well region has a central portion and two horizontally abutting end portions. The central portion has a higher concentration of a first conductivity type dopant than the two horizontally abutting end portions.

Abstract translation: 提供了具有高器件性能和改善的短沟道效应的半导体结构。 特别地，提供了一种金属氧化物半导体场效应晶体管（MOFET），其包括在该结构的反转层内的低掺杂浓度; 反型层是形成在半导体衬底的一部分顶上的外延半导体层。 该结构还包括在反转层下面的第一导电类型的阱区，其中阱区具有中心部分和两个水平邻接的端部。 中心部分具有比两个水平邻接端部更高的第一导电类型掺杂剂的浓度。

公开(公告)号：US20130001691A1

公开(公告)日：2013-01-03

申请号：US13381075

申请日：2011-08-25

Applicant: Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

Inventor： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

IPC: H01L29/772 ,  H01L21/283

CPC classification number: H01L29/41733 ,  H01L21/76816 ,  H01L21/76882 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/458 ,  H01L29/66636 ,  H01L29/66772 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method for manufacturing a semiconductor structure, which comprises: providing an SOI substrate, and forming a gate structure on the SOI substrate; etching an SOI layer and a BOX layer of the SOI substrates on both sides of the gate structure, so as to form trenches exposing the BOX layer and extending partially into the BOX layer; forming metal sidewall spacers on sidewalls of the trenches, wherein the metal sidewall spacers is in contact with the SOI layer under the gate structure; forming an insulating layer filling partially the trenches, and forming a dielectric layer to cover the gate structure and the insulating layer; etching the dielectric layer to form first contact through holes that expose at least partially the insulating layer, and etching the insulating layer from the first contact through holes to form second contact through holes that expose at least partially the metal sidewall spacer; filling the first contact through holes and the second contact through holes to form contact vias, which are in contact with the metal sidewall spacers. The method provided by the present invention is capable of improving performance of semiconductor devices and alleviating manufacturing difficulty at the mean time.

Abstract translation: 本发明提供一种制造半导体结构的方法，其包括：提供SOI衬底，并在SOI衬底上形成栅极结构; 在栅极结构的两侧蚀刻SOI衬底的SOI层和BOX层，以形成露出BOX层并部分延伸到BOX层的沟槽; 在所述沟槽的侧壁上形成金属侧壁间隔物，其中所述金属侧壁间隔物与所述栅极结构下的所述SOI层接触; 形成部分填充沟槽的绝缘层，形成覆盖栅结构和绝缘层的电介质层; 蚀刻所述介电层以形成至少部分地暴露所述绝缘层的第一接触通孔，以及从所述第一接触通孔蚀刻所述绝缘层以形成至少部分地暴露所述金属侧壁间隔物的第二接触通孔; 通过孔和第二接触通孔填充第一接触件以形成与金属侧壁间隔件接触的接触通孔。 本发明提供的方法能够提高半导体装置的性能，同时能够减轻制造难度。

公开(公告)号：US08343818B2

公开(公告)日：2013-01-01

申请号：US12687287

申请日：2010-01-14

Applicant: Huilong Zhu ,  Zhijiong Luo ,  Qingqing Liang ,  Haizhou Yin

Inventor： Huilong Zhu ,  Zhijiong Luo ,  Qingqing Liang ,  Haizhou Yin

IPC: H01L21/84

CPC classification number: H01L21/187 ,  H01L21/6835 ,  H01L21/84 ,  H01L27/12 ,  H01L29/1083 ,  H01L2221/6835 ,  H01L2221/68368

Abstract: A method of forming an electrical device is provided that includes forming at least one semiconductor device on a first semiconductor layer of the SOI substrate. A handling structure is formed contacting the at least one semiconductor device and the first semiconductor layer. A second semiconductor layer and at least a portion of the dielectric layer of the SOI substrate are removed to provide a substantially exposed surface of the first semiconductor layer. A retrograded well may be formed by implanting dopant through the substantially exposed surface of the first semiconductor layer into a first thickness of the semiconductor layer that extends from the substantially exposed surface of the semiconductor layer, wherein a remaining thickness of the semiconductor layer is substantially free of the retrograded well dopant. The retrograded well may be laser annealed.