公开(公告)号：US06391769B1

公开(公告)日：2002-05-21

申请号：US09525154

申请日：2000-03-14

Applicant: Jong-myeong Lee ,  Hyun-seok Lim ,  Byung-hee Kim ,  Gil-heyun Choi ,  Sang-in Lee

Inventor： Jong-myeong Lee ,  Hyun-seok Lim ,  Byung-hee Kim ,  Gil-heyun Choi ,  Sang-in Lee

IPC: H01L214763

CPC classification number: H01L21/76855 ,  H01L21/28562 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76882 ,  H01L21/76888 ,  H01L2221/1089

Abstract: A method for forming a metal interconnection filling a contact hole or a groove having a high aspect ratio, and a contact structure fabricated thereby. An interdielectric layer pattern, having a recessed region serving as a contact hole, a via hole or a groove, is formed on a semiconductor substrate. A barrier metal layer is formed on the entire surface of the resultant structure where the interdielectric layer pattern is formed. An anti-nucleation layer is selectively formed only on the non-recessed region of the barrier metal layer. The anti-nucleation layer is formed by forming a metal layer overlying the barrier metal layer in regions other than the recessed region, and then spontaneously oxidizing the metal layer in a vacuum. Also, the anti-nucleation layer may be formed by in-situ forming the barrier metal layer and the metal layer and then oxidizing the metal layer by an annealing process. Subsequently, a metal plug is selectively formed in the recessed region, surrounded by the barrier metal layer, thereby forming a metal interconnection for completely filling the contact hole or the groove having a high aspect ratio. A metal liner may be formed instead of the metal plug, followed by forming a metal layer filling the region surrounded by the metal liner, thereby forming a metal interconnection for completely filling the contact hole or groove having a high aspect ratio.

Abstract translation: 一种用于形成填充高纵横比的接触孔或槽的金属互连的方法，以及由此制造的接触结构。 在半导体衬底上形成具有用作接触孔的凹陷区域，通孔或沟槽的电介质层图案。 在形成介电层图案的所得结构的整个表面上形成阻挡金属层。 仅在阻挡金属层的非凹陷区域选择性地形成抗成核层。 通过在除了凹陷区域之外的区域中形成覆盖阻挡金属层的金属层，然后在真空中自发氧化金属层，形成抗成核层。 此外，抗成核层可以通过原位形成阻挡金属层和金属层，然后通过退火处理来氧化金属层而形成。 随后，在由阻挡金属层包围的凹陷区域中选择性地形成金属插塞，从而形成用于完全填充接触孔或具有高纵横比的沟槽的金属互连。 可以形成金属衬垫而不是金属插塞，随后形成填充由金属衬垫包围的区域的金属层，从而形成用于完全填充具有高纵横比的接触孔或槽的金属互连。

公开(公告)号：US08889543B2

公开(公告)日：2014-11-18

申请号：US13795807

申请日：2013-03-12

Applicant: Jong-Min Baek ,  In-Sun Park ,  Jong-Myeong Lee ,  Jong-Won Hong ,  Hei-Seung Kim ,  Jung-Soo Yoon

Inventor： Jong-Min Baek ,  In-Sun Park ,  Jong-Myeong Lee ,  Jong-Won Hong ,  Hei-Seung Kim ,  Jung-Soo Yoon

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76885

Abstract: A method of fabricating a semiconductor device includes forming switching devices on a substrate. A lower structure is formed in the substrate having the switching devices. A lower conductive layer is formed on the lower structure. Sacrificial mask patterns are formed on the lower conductive layer. Lower conductive patterns are formed by etching the lower conductive layer using the sacrificial mask patterns as an etch mask. An interlayer insulating layer is formed on the substrate having the lower conductive patterns. Interlayer insulating patterns are formed by planarizing the interlayer insulating layer until the sacrificial mask patterns are exposed. Openings exposing the lower conductive patterns are formed by removing the exposed sacrificial mask patterns. Upper conductive patterns self-aligned with the lower conductive patterns are formed in the openings.

Abstract translation: 制造半导体器件的方法包括在衬底上形成开关器件。 在具有开关装置的基板中形成下部结构。 下导电层形成在下结构上。 牺牲掩模图案形成在下导电层上。 通过使用牺牲掩模图案作为蚀刻掩模蚀刻下导电层来形成下导电图案。 在具有较低导电图案的基板上形成层间绝缘层。 通过平坦化层间绝缘层直到牺牲掩模图案曝光来形成层间绝缘图案。 通过去除暴露的牺牲掩模图案来形成露出下导电图案的开口。 在开口中形成与下导电图案自对准的上导电图案。

公开(公告)号：US20130267088A1

公开(公告)日：2013-10-10

申请号：US13795807

申请日：2013-03-12

Applicant: JONG-MIN BAEK ,  IN-SUN PARK ,  JONG-MYEONG LEE ,  JONG-WON HONG ,  HEI-SEUNG KIM ,  JUNG-SOO YOON

Inventor： JONG-MIN BAEK ,  IN-SUN PARK ,  JONG-MYEONG LEE ,  JONG-WON HONG ,  HEI-SEUNG KIM ,  JUNG-SOO YOON

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76885

Abstract: A method of fabricating a semiconductor device includes forming switching devices on a substrate. A lower structure is formed in the substrate having the switching devices. A lower conductive layer is formed on the lower structure. Sacrificial mask patterns are formed on the lower conductive layer. Lower conductive patterns are formed by etching the lower conductive layer using the sacrificial mask patterns as an etch mask. An interlayer insulating layer is formed on the substrate having the lower conductive patterns. Interlayer insulating patterns are formed by planarizing the interlayer insulating layer until the sacrificial mask patterns are exposed. Openings exposing the lower conductive patterns are formed by removing the exposed sacrificial mask patterns. Upper conductive patterns self-aligned with the lower conductive patterns are formed in the openings.

Abstract translation: 制造半导体器件的方法包括在衬底上形成开关器件。 在具有开关装置的基板中形成下部结构。 下导电层形成在下结构上。 牺牲掩模图案形成在下导电层上。 通过使用牺牲掩模图案作为蚀刻掩模蚀刻下导电层来形成下导电图案。 在具有较低导电图案的基板上形成层间绝缘层。 通过平坦化层间绝缘层直到牺牲掩模图案曝光来形成层间绝缘图案。 通过去除暴露的牺牲掩模图案来形成露出下导电图案的开口。 在开口中形成与下导电图案自对准的上导电图案。

公开(公告)号：US08404579B2

公开(公告)日：2013-03-26

申请号：US12960150

申请日：2010-12-03

Applicant: Sang-Hoon Ahn ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Sang-Don Nam ,  Kyu-Hee Han

Inventor： Sang-Hoon Ahn ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Sang-Don Nam ,  Kyu-Hee Han

IPC: H01L21/44

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fuse base insulating region, for example, an insulating interlayer or a compensation region disposed in an insulating interlayer, is formed on a substrate. An etch stop layer is formed on the fuse base insulating region and forming an insulating interlayer having a lower dielectric constant than the first fuse base insulating region on the etch stop layer. A trench extending through the insulating interlayer and the etch stop layer and at least partially into the fuse base insulating region is formed. A fuse is formed in the trench. The fuse base insulating region may have a greater mechanical strength and/or density than the second insulating interlayer.

Abstract translation: 在衬底上形成熔丝基底绝缘区域，例如绝缘中间层或设置在绝缘中间层中的补偿区域。 在熔丝基底绝缘区上形成蚀刻停止层，形成绝缘中间层，该绝缘中间层的介电常数比蚀刻停止层上的第一熔丝基底绝缘区低。 形成了延伸穿过绝缘中间层和蚀刻停止层并且至少部分地进入熔丝基底绝缘区域的沟槽。 在沟槽中形成熔丝。 保险丝座绝缘区域可具有比第二绝缘中间层更大的机械强度和/或密度。

公开(公告)号：US08304343B2

公开(公告)日：2012-11-06

申请号：US13240109

申请日：2011-09-22

Applicant: Kyung-In Choi ,  Hyeon-Deok Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee

Inventor： Kyung-In Choi ,  Hyeon-Deok Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee

IPC: H01L21/768

CPC classification number: H01L21/76814 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76856 ,  H01L27/11526 ,  H01L27/11543 ,  H01L27/11546 ,  H01L27/11548

Abstract: In a method of manufacturing a metal wiring structure, a first metal wiring and a first barrier layer are formed on a substrate, and the first barrier layer is nitridated. An insulating interlayer is formed on the substrate so as to extend over the first metal wiring and the first barrier layer. Part of the insulating interlayer is removed to form a hole exposing at least part of the first metal wiring and part of the first barrier layer. A nitridation plasma treatment is performed on the exposed portion of the first barrier layer. A second barrier layer is formed along the bottom and sides of the hole. A plug is formed on the second barrier layer to fill the hole.

Abstract translation: 在制造金属布线结构的方法中，在基板上形成第一金属布线和第一阻挡层，并且对第一阻挡层进行氮化。 绝缘中间层形成在基板上，以便延伸越过第一金属布线和第一阻挡层。 去除部分绝缘中间层以形成露出第一金属布线和第一阻挡层的一部分的至少一部分的孔。 在第一阻挡层的暴露部分上进行氮化等离子体处理。 沿着孔的底部和侧面形成第二阻挡层。 在第二阻挡层上形成插塞以填充孔。

公开(公告)号：US08278207B2

公开(公告)日：2012-10-02

申请号：US12688557

申请日：2010-01-15

Applicant: Jin-Ho Park ,  Gil-Heyun Choi ,  Byung-Lyul Park ,  Jong-Myeong Lee ,  Zung-Sun Choi ,  Hye-Kyung Jung

Inventor： Jin-Ho Park ,  Gil-Heyun Choi ,  Byung-Lyul Park ,  Jong-Myeong Lee ,  Zung-Sun Choi ,  Hye-Kyung Jung

IPC: H01L21/4763

CPC classification number: H01L21/76846 ,  H01L21/28562 ,  H01L21/76856 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L27/10855 ,  H01L27/11521 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device can include an insulation layer on that is on a substrate on which a plurality of lower conductive structures are formed, where the insulation layer has an opening. A barrier layer is on a sidewall and a bottom of the opening of the insulation layer, where the barrier layer includes a first barrier layer in which a constituent of a first deoxidizing material is richer than a metal material in the first barrier layer and a second barrier layer in which a metal material in the second barrier layer is richer than a constituent of a second deoxidizing material. An interconnection is in the opening of which the sidewall and the bottom are covered with the barrier layer, the interconnection is electrically connected to the lower conductive structure.

Abstract translation: 半导体器件可以包括在其上形成有多个下导电结构的基板上的绝缘层，其中绝缘层具有开口。 阻挡层位于绝缘层的开口的侧壁和底部上，其中阻挡层包括第一阻挡层，第一脱氧材料的成分比第一阻挡层中的金属材料更富，第二阻隔层 阻挡层，其中第二阻挡层中的金属材料比第二脱氧材料的成分更富。 互连在其开口中，侧壁和底部被阻挡层覆盖，互连电连接到下导电结构。

公开(公告)号：US20110003476A1

公开(公告)日：2011-01-06

申请号：US12829776

申请日：2010-07-02

Applicant: Jong-ho Yun ,  Gil-heyun Choi ,  Jong-myeong Lee

Inventor： Jong-ho Yun ,  Gil-heyun Choi ,  Jong-myeong Lee

IPC: H01L21/768

CPC classification number: H01L21/76895 ,  H01L21/288 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76879

Abstract: A semiconductor device in which an increase of contact resistance Rc between a metal contact and a plug due to misalignment between the metal contact and the plug can be reduced and the difficulty of a Cu filling process during the process of forming the plug may be reduced. The semiconductor device includes a substrate including an active area and a device isolation layer; a metal contact that is formed on the substrate and is electrically connected to the active area; a landing pad formed on the metal contact by electroless plating; and a plug that is formed on the landing pad and is electrically connected to the metal contact via the landing pad.

Abstract translation: 可以减少由于金属接触和插塞之间的未对准而导致金属接触和插塞之间的接触电阻Rc增大的半导体器件，并且可以减少在形成插头的过程中Cu填充过程的困难。 半导体器件包括：衬底，其包括有源区和器件隔离层; 金属接触件，其形成在所述基板上并电连接到所述有源区域; 通过无电镀形成在金属接触件上的着陆垫; 以及形成在所述着陆板上并且经由所述着陆垫电连接到所述金属接触件的插头。

公开(公告)号：US20100151672A1

公开(公告)日：2010-06-17

申请号：US12711812

申请日：2010-02-24

Applicant: Kyung-In Choi ,  Sang-Woo Lee ,  Jong-Myeong Lee ,  Jong-Won Hong ,  Hyun-Bae Lee

Inventor： Kyung-In Choi ,  Sang-Woo Lee ,  Jong-Myeong Lee ,  Jong-Won Hong ,  Hyun-Bae Lee

IPC: H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76846 ,  H01L21/76858 ,  H01L23/53223 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming a metal interconnection structure are provided. The methods include forming an insulating layer on a semiconductor substrate including a first metal interconnection. The insulating layer is patterned to form an opening that exposes the first metal interconnection. A first diffusion barrier layer is formed on the exposed first metal interconnection. After forming the first diffusion barrier layer, a second diffusion barrier layer is formed on the first diffusion barrier layer in the opening, the second diffusion barrier layer contacting a sidewall of the opening. A second metal interconnection is formed on the second diffusion barrier layer.

Abstract translation: 提供形成金属互连结构的方法。 所述方法包括在包括第一金属互连的半导体衬底上形成绝缘层。 图案化绝缘层以形成露出第一金属互连的开口。 在暴露的第一金属互连上形成第一扩散阻挡层。 在形成第一扩散阻挡层之后，在开口中的第一扩散阻挡层上形成第二扩散阻挡层，第二扩散阻挡层与开口的侧壁接触。 第二金属互连形成在第二扩散阻挡层上。

公开(公告)号：US20080296696A1

公开(公告)日：2008-12-04

申请号：US12127208

申请日：2008-05-27

Applicant: Jung-Ho Yun ,  Gil-heyun Choi ,  Jong-Myeong Lee

Inventor： Jung-Ho Yun ,  Gil-heyun Choi ,  Jong-Myeong Lee

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/823835

Abstract: Provided are a semiconductor device and a method of forming the same. The method includes forming an interlayer dielectric on a semiconductor substrate, forming a contact hole in the interlayer dielectric to expose the semiconductor substrate, forming a metal pattern including a dopant on the exposed semiconductor substrate, and performing a heat treatment process to react the semiconductor substrate with the metal pattern to form a metal silicide pattern. The heat treatment process includes diffuses the dopant into the semiconductor substrate.

Abstract translation: 提供半导体器件及其形成方法。 该方法包括在半导体衬底上形成层间电介质，在层间电介质中形成接触孔以露出半导体衬底，在暴露的半导体衬底上形成包括掺杂剂的金属图案，并进行热处理工艺以使半导体衬底 与金属图案形成金属硅化物图案。 热处理工艺包括将掺杂剂扩散到半导体衬底中。

公开(公告)号：US20080054468A1

公开(公告)日：2008-03-06

申请号：US11892089

申请日：2007-08-20

Applicant: Kyung-In Choi ,  Gil-Heyun Choi ,  Sang-Woo Lee ,  Jong-Myeong Lee ,  Jong-Won Hong ,  Hyun-Bae Lee

Inventor： Kyung-In Choi ,  Gil-Heyun Choi ,  Sang-Woo Lee ,  Jong-Myeong Lee ,  Jong-Won Hong ,  Hyun-Bae Lee

IPC: H01L23/52 ,  H01L21/4763

CPC classification number: H01L21/76868 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An example embodiment provides a method of forming a conductive pattern in a semiconductor device. The method includes forming one or more dielectric layers over a first conductive pattern formed on a substrate; forming an opening in the one or more dielectric layers to expose a portion of the first conductive pattern, forming a growth promoting layer over the exposed portion of the first conductive pattern and the one or more dielectric layers, forming a growth inhibiting layer over a portion of the growth promoting layer, and forming the second conductive layer in the opening.

Abstract translation: 示例性实施例提供了在半导体器件中形成导电图案的方法。 该方法包括在形成在衬底上的第一导电图案上形成一个或多个电介质层; 在所述一个或多个电介质层中形成开口以暴露所述第一导电图案的一部分，在所述第一导电图案和所述一个或多个介电层的暴露部分上形成增长促进层，在所述第一导电图案的一部分上形成生长抑制层 的生长促进层，并且在开口中形成第二导电层。