公开(公告)号：US20160086874A1

公开(公告)日：2016-03-24

申请号：US14858572

申请日：2015-09-18

Applicant: Ju-Il Choi ,  Kwang-Jin Moon ,  Byung-Lyul Park ,  Jin-Ho An ,  Atsushi Fujisaki

Inventor： Ju-Il Choi ,  Kwang-Jin Moon ,  Byung-Lyul Park ,  Jin-Ho An ,  Atsushi Fujisaki

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/03618 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/05155 ,  H01L2224/05546 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05564 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/13023 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16013 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/01047

Abstract: A semiconductor device can include a substrate that has a surface. A via structure can extend through the substrate toward the surface of the substrate, where the via structure includes an upper surface. A pad structure can be on the surface of the substrate, where the pad structure can include a lower surface having at least one protrusion that is configured to protrude toward the upper surface of the via structure.

Abstract translation: 半导体器件可以包括具有表面的衬底。 通孔结构可以延伸穿过衬底朝向衬底的表面，其中通孔结构包括上表面。 衬垫结构可以在衬底的表面上，其中衬垫结构可以包括具有至少一个突起的下表面，其被配置为朝向通孔结构的上表面突出。

公开(公告)号：US08847399B2

公开(公告)日：2014-09-30

申请号：US13287317

申请日：2011-11-02

Applicant: Byung-Lyul Park ,  Gil-Heyun Choi ,  Suk-Chul Bang ,  Kwang-Jin Moon ,  Dong-Chan Lim ,  Deok-Young Jung

Inventor： Byung-Lyul Park ,  Gil-Heyun Choi ,  Suk-Chul Bang ,  Kwang-Jin Moon ,  Dong-Chan Lim ,  Deok-Young Jung

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/40 ,  H01L21/768 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L21/76898 ,  H01L21/76801 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: For forming a semiconductor device, a via structure is formed through at least one dielectric layer and at least a portion of a substrate. In addition, a protective buffer layer is formed onto the via structure. Furthermore, a conductive structure for an integrated circuit is formed over the substrate after forming the via structure and the protective buffer layer, with the conductive structure not being formed over the via structure. Thus, deterioration of the conductive and via structures is minimized.

Abstract translation: 为了形成半导体器件，通过至少一个电介质层和至少一部分衬底形成通孔结构。 此外，在通孔结构上形成保护缓冲层。 此外，在形成通孔结构和保护缓冲层之后，在衬底上形成用于集成电路的导电结构，其中导电结构不在过孔结构上形成。 因此，导电和通孔结构的劣化被最小化。

公开(公告)号：US20140217603A1

公开(公告)日：2014-08-07

申请号：US13756593

申请日：2013-02-01

Applicant: Kwang-jin Moon ,  Pil-Kyu Kang ,  Dae-Lok Bae ,  Gil-Heyun Choi ,  Byung-Lyul Park ,  Dong-Chan Lim ,  Deok-Young Jung

Inventor： Kwang-jin Moon ,  Pil-Kyu Kang ,  Dae-Lok Bae ,  Gil-Heyun Choi ,  Byung-Lyul Park ,  Dong-Chan Lim ,  Deok-Young Jung

IPC: H01L23/498

CPC classification number: H01L23/49827 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a via structure and a conductive structure. The via structure has a surface with a planar portion and a protrusion portion. The conductive structure is formed over at least part of the planar portion and not over at least part of the protrusion portion of the via structure. For example, the conductive structure is formed only onto the planar portion and not onto any of the protrusion portion for forming high quality connection between the conductive structure and the via structure.

Abstract translation: 半导体器件包括通孔结构和导电结构。 通孔结构具有平坦部分和突出部分的表面。 导电结构形成在平面部分的至少一部分上，而不是在通孔结构的突出部分的至少一部分之上。 例如，导电结构仅形成在平面部分上，而不形成在任何突出部分上，用于在导电结构和通孔结构之间形成高质量的连接。

公开(公告)号：US20140070426A1

公开(公告)日：2014-03-13

申请号：US13926616

申请日：2013-06-25

Applicant: Jae-hwa Park ,  Kwang-jin Moon ,  Byung-Iyul Park

Inventor： Jae-hwa Park ,  Kwang-jin Moon ,  Byung-Iyul Park

IPC: H01L23/48 ,  H01L21/48

CPC classification number: H01L23/481 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/49827 ,  H01L23/53238 ,  H01L23/552 ,  H01L25/0657 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/11009 ,  H01L2224/13 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Integrated circuit devices are provided. The integrated circuit devices may include a via structure including a conductive plug, a conductive barrier layer spaced apart from the conductive plug, and an insulating layer between the conductive plug and conductive barrier layer. Related methods of forming integrated circuit devices are also provided.

Abstract translation: 提供集成电路设备。 集成电路器件可以包括通孔结构，其包括导电插塞，与导电插塞间隔开的导电阻挡层，以及在导电插塞和导电阻挡层之间的绝缘层。 还提供了形成集成电路器件的相关方法。

公开(公告)号：US08592310B2

公开(公告)日：2013-11-26

申请号：US13240040

申请日：2011-09-22

Applicant: Byung-Lyul Park ,  Gil-Heyun Choi ,  Suk-Chul Bang ,  Kwang-Jin Moon ,  Dong-Chan Lim ,  Deok-Young Jung

Inventor： Byung-Lyul Park ,  Gil-Heyun Choi ,  Suk-Chul Bang ,  Kwang-Jin Moon ,  Dong-Chan Lim ,  Deok-Young Jung

IPC: H01L21/44

CPC classification number: H01L21/76898 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05018 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05609 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/01029 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In methods of manufacturing a semiconductor device, a substrate having a first surface and a second surface opposite to the first surface is prepared. A sacrificial layer pattern is formed in a region of the substrate that a through electrode will be formed. The sacrificial layer pattern extends from the first surface of the substrate in a thickness direction of the substrate. An upper wiring layer is formed on the first surface of the substrate. The upper wiring layer includes a wiring on the sacrificial layer pattern. The second surface of the substrate is partially removed to expose the sacrificial layer pattern. The sacrificial layer pattern is removed from the second surface of the substrate to form an opening that exposes the wiring. A through electrode is formed in the opening to be electrically connected to the wiring.

Abstract translation: 在制造半导体器件的方法中，制备具有与第一表面相对的第一表面和第二表面的衬底。 在基板的形成有通孔的区域中形成牺牲层图案。 牺牲层图案在基板的厚度方向上从基板的第一表面延伸。 在衬底的第一表面上形成上部布线层。 上部布线层包括牺牲层图案上的布线。 部分去除衬底的第二表面以暴露牺牲层图案。 牺牲层图案从基板的第二表面移除以形成露出布线的开口。 通孔形成在开口中以与布线电连接。

公开(公告)号：US08294220B2

公开(公告)日：2012-10-23

申请号：US12685265

申请日：2010-01-11

Applicant: Hyun-Su Kim ,  Kwang-Jin Moon ,  Sang-Woo Lee ,  Eun-Ok Lee ,  Ho-Ki Lee

Inventor： Hyun-Su Kim ,  Kwang-Jin Moon ,  Sang-Woo Lee ,  Eun-Ok Lee ,  Ho-Ki Lee

IPC: H01L23/50

CPC classification number: H01L21/76855 ,  H01L21/28556 ,  H01L21/76843

Abstract: Contacts having different characteristics may be created by forming a first silicide layer over a first device region of a substrate, and then forming a second silicide layer over a second device region while simultaneously further forming the first silicide layer. A first contact hole may be formed in a dielectric layer over a first device region of a substrate. A silicide layer may then be formed in the first contact hole. A second contact hole may be formed after the first contact hole and silicide layer is formed. A second silicidation may then be performed in the first and second contact holes.

Abstract translation: 可以通过在衬底的第一器件区域上形成第一硅化物层，然后在第二器件区域上形成第二硅化物层，同时进一步形成第一硅化物层来产生具有不同特性的触点。 可以在衬底的第一器件区域上的介电层中形成第一接触孔。 然后可以在第一接触孔中形成硅化物层。 可以在形成第一接触孔和硅化物层之后形成第二接触孔。 然后可以在第一和第二接触孔中执行第二硅化。

公开(公告)号：US20110316168A1

公开(公告)日：2011-12-29

申请号：US12913748

申请日：2010-10-27

Applicant: Kwang-Jin Moon ,  Pil-Kyu Kang ,  Dae-Lok Bae ,  Gil-Heyun Choi ,  Byung-Lyul Park ,  Dong-Chan Lim ,  Deok-Young Jung

Inventor： Kwang-Jin Moon ,  Pil-Kyu Kang ,  Dae-Lok Bae ,  Gil-Heyun Choi ,  Byung-Lyul Park ,  Dong-Chan Lim ,  Deok-Young Jung

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/528 ,  H01L2224/16146 ,  H01L2225/06541 ,  H01L2924/01327 ,  H01L2924/00

Abstract: A semiconductor device includes a via structure and a conductive structure. The via structure has a surface with a planar portion and a protrusion portion. The conductive structure is formed over at least part of the planar portion and not over at least part of the protrusion portion of the via structure. For example, the conductive structure is formed only onto the planar portion and not onto any of the protrusion portion for forming high quality connection between the conductive structure and the via structure.

Abstract translation: 半导体器件包括通孔结构和导电结构。 通孔结构具有平坦部分和突出部分的表面。 导电结构形成在平面部分的至少一部分上，而不是在通孔结构的突出部分的至少一部分之上。 例如，导电结构仅形成在平面部分上，而不形成在任何突出部分上，用于在导电结构和通孔结构之间形成高质量的连接。

公开(公告)号：US20070246783A1

公开(公告)日：2007-10-25

申请号：US11649890

申请日：2007-01-05

Applicant: Kwang-jin Moon ,  Hyun-su Kim ,  Sang-woo Lee ,  Ho-ki Lee ,  Eun-ok Lee ,  Sung-tae Kim

Inventor： Kwang-jin Moon ,  Hyun-su Kim ,  Sang-woo Lee ,  Ho-ki Lee ,  Eun-ok Lee ,  Sung-tae Kim

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/44

CPC classification number: H01L29/66666 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/1037 ,  H01L29/42376 ,  H01L29/7827 ,  H01L29/7831

Abstract: A method of manufacturing a semiconductor device includes forming a pillar-shaped active region by etching a portion of a semiconductor substrate, forming a blocking film selectively exposing a sidewall of a lower portion of the pillar-shaped active region, and forming a bit-line selectively on the exposed sidewall of the lower portion of the pillar-shaped active region.

Abstract translation: 一种制造半导体器件的方法包括通过蚀刻半导体衬底的一部分形成柱状有源区，形成选择性地暴露柱状有源区的下部的侧壁的阻挡膜，并形成位线 选择性地在柱状活性区域的下部的暴露的侧壁上。

公开(公告)号：US20070197015A1

公开(公告)日：2007-08-23

申请号：US11787468

申请日：2007-04-17

Applicant: Hee-sook Park ,  Gil-heyun Choi ,  Sang-bum Kang ,  Seong-geon Park ,  Kwang-jin Moon

Inventor： Hee-sook Park ,  Gil-heyun Choi ,  Sang-bum Kang ,  Seong-geon Park ,  Kwang-jin Moon

IPC: H01L21/44

CPC classification number: H01L21/76843 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76858

Abstract: A metal contact in a semiconductor device is formed by forming an insulating layer having a contact hole therein on a silicon substrate. A cobalt layer is formed on a bottom and inner walls of the contact hole. A cobalt silicide layer is formed at the bottom of the contact hole while forming a titanium layer on the cobalt layer. A plug is formed on the titanium layer so as to fill the contact hole.

公开(公告)号：US20070105358A1

公开(公告)日：2007-05-10

申请号：US11355112

申请日：2006-02-14

Applicant: Hyun-Su Kim ,  Kwang-Jin Moon ,  Sang-Woo Lee ,  Eun-Ok Lee ,  Ho-Ki Lee

Inventor： Hyun-Su Kim ,  Kwang-Jin Moon ,  Sang-Woo Lee ,  Eun-Ok Lee ,  Ho-Ki Lee

IPC: H01L21/44

CPC classification number: H01L21/76855 ,  H01L21/28556 ,  H01L21/76843

Abstract: Contacts having different characteristics may be created by forming a first silicide layer over a first device region of a substrate, and then forming a second silicide layer over a second device region while simultaneously further forming the first silicide layer. A first contact hole may be formed in a dielectric layer over a first device region of a substrate. A silicide layer may then be formed in the first contact hole. A second contact hole may be formed after the first contact hole and silicide layer is formed. A second silicidation may then be performed in the first and second contact holes.

Abstract translation: 可以通过在衬底的第一器件区域上形成第一硅化物层，然后在第二器件区域上形成第二硅化物层，同时进一步形成第一硅化物层来产生具有不同特性的触点。 可以在衬底的第一器件区域上的介电层中形成第一接触孔。 然后可以在第一接触孔中形成硅化物层。 可以在形成第一接触孔和硅化物层之后形成第二接触孔。 然后可以在第一和第二接触孔中执行第二硅化。