Method for improved process latitude by elongated via integration

    公开(公告)号:US20060006546A1

    公开(公告)日:2006-01-12

    申请号:US10887086

    申请日:2004-07-09

    Inventor: Matthew Colburn

    Abstract: Interconnect dual damascene structure are fabricated by depositing on a layer of at least one dielectric, a mask forming layer for providing the via-level mask layer of the dual damascene structures; creating an elongated via pattern in the via-level mask layer; depositing a layer of line-level dielectric and creating a line pattern through the layer of line-level dielectric, and transferring the line pattern through the projected intersection of the elongated via-level pattern and of the line-level pattern thereby generating an aligned dual damascene structure. A conductive liner layer is deposited in the dual damascene structure followed by filling the dual damascene structure with a conductive fill metal to form a set of metal lines. The metal and liner layers are planarized.

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