ELECTRICAL DUOBINARY SOFT INFORMATION RECEIVER FOR NRZ MODULATION FIBER TRANSMISSION

    公开(公告)号:US20220190931A1

    公开(公告)日:2022-06-16

    申请号:US17594357

    申请日:2020-04-09

    Inventor: Rainer STROBEL

    Abstract: A receiver circuit is disclosed and is configured to receive an optical signal. The receiver circuit includes a receiving circuit configured to receive the optical signal and convert the optical signal from a duobinary signal format into a binary signal based on a plurality of decision thresholds. The receiver circuit also includes a clock data recovery circuit configured to sample the binary signal per data period at a first time instant based on a predetermined clock data recovery technique, and sample the binary signal per data period at a second time instant offset from the first instant, as well as determine an intermediate sample based on an offset for decoding a transmitted bit sequence according to soft information based on the samples.

    DISTORTION-OPTIMIZED TRANSMISSION IN HYBRID FIBER COAX NETWORKS

    公开(公告)号:US20220149891A1

    公开(公告)日:2022-05-12

    申请号:US17434383

    申请日:2020-02-26

    Abstract: A node circuit associated with a hybrid fiber coax (HFC) network is disclosed. The node circuit includes an optimizer circuit configured to process a plurality of signal-to-noise ratio (SNR) values associated with a plurality of subcarriers, respectively, associated with a set of cable modem (CM) circuits coupled to the node circuit. In some embodiments, the plurality of subcarriers comprises subcarriers that are allocated to the set of CM circuits for communication with the node circuit. In some embodiments, the optimizer circuit is further configured to determine an optimal transmit power of the node circuit, based on the plurality of SNR values and a distortion model of a transmitter circuit associated with the node circuit. In some embodiments, the distortion model defines a transmitter distortion associated with the transmitter circuit.

    DATA PACKET PROCESSING SYSTEM ON A CHIP

    公开(公告)号:US20220038385A1

    公开(公告)日:2022-02-03

    申请号:US17451487

    申请日:2021-10-19

    Abstract: An on-chip data packet processing method and corresponding integrated circuit, wherein data packets are received at an ingress port and processed with an on-chip wire-speed engine. The processing comprises adding metadata to the data packets, forwarding the processed data to an on-chip QoS unit, altering the metadata of the data packets and/or providing further metadata to the data packets. The data packets are forwarded from the on-chip QoS unit to an on-chip data consumer. If the data consumer is a processing unit the data packets are processed in a first processing step, redirected from the processing unit to the QoS unit and the step of forwarding the data packets to an on-chip data consumer is repeated.

    Receiver filtering
    44.
    发明授权

    公开(公告)号:US11201693B2

    公开(公告)日:2021-12-14

    申请号:US16860587

    申请日:2020-04-28

    Inventor: YouZhe Fan

    Abstract: A receiver may include a first filter configured to generate a first estimation of a symbol of a received signal and a second filter configured to generate a second estimation of the symbol of the received signal. The receiver may also include a decoder configured to decode the symbol using one of the first estimation and the second estimation and a decision circuitconfigured to select one of the first estimation and the second estimation to provide to the decoder for decoding of the symbol based on a comparison of the first estimation to an estimation threshold.

    ESTABLISHMENT OF NETWORK CONNECTIONS

    公开(公告)号:US20210377311A1

    公开(公告)日:2021-12-02

    申请号:US17399038

    申请日:2021-08-10

    Abstract: A method for establishing network connections includes connecting a device to a first network, retrieving voice input of a user, sending a message including data related to the voice input to at least one gateway device on the first network, receiving configuration data for a second network via the first network in response to the message, and establishing a connection of the device to the second network using the configuration data received via the first network. Furthermore, an electronic device, a network gateway device and a system are defined.

    RECEIVER FILTERING
    46.
    发明申请

    公开(公告)号:US20210336718A1

    公开(公告)日:2021-10-28

    申请号:US16860587

    申请日:2020-04-28

    Inventor: YouZhe FAN

    Abstract: receiver may include a first filter configured to generate a first estimation of a symbol of a received signal and a second filter configured to generate a second estimation of the symbol of the received signal. The receiver may also include a decoder configured to decode the symbol using one of the first estimation and the second estimation and a decision circuit configured to select one of the first estimation and the second estimation to provide to the decoder for decoding of the symbol based on a comparison of the first estimation to an estimation threshold.

    Echo cancellation leveraging out-of-band frequencies

    公开(公告)号:US11005526B2

    公开(公告)日:2021-05-11

    申请号:US16358093

    申请日:2019-03-19

    Abstract: An electronic communication device comprises echo cancellation circuitry and signal modification circuitry. The echo cancellation circuitry may be operable to generate a first signal that approximates interference present in a second signal. The signal modification circuitry may be operable to generate a first cancellation signal in a frequency band that is not used on a communication medium over which the electronic communication device is configured to communicate. The signal modification circuitry may be operable to combine the first cancellation signal with the first signal, wherein the combining of the signals results in a modified first signal that has a lower crest factor and/or peak-to-average power ratio than the first signal. The signal modification circuitry may be operable to combine the modified first signal with the second signal to reduce interference present in the second signal.

    State grouping methodologies to compress transitions in a deterministic automata

    公开(公告)号:US10862903B2

    公开(公告)日:2020-12-08

    申请号:US15454274

    申请日:2017-03-09

    Abstract: A hardware system for signature matching in a distributed network is disclosed. The hardware system comprises a network processor and a memory. The network processor is configured to perform horizontal compression on a state table using bitmaps, wherein the state table has a plurality of states and state transitions. The processor is also configured to perform a first grouping of states of the state table using the bitmaps to generate a first one or more sets of states, perform a second grouping of states of the state table based on the first one or more sets of states and a transition threshold to generate a second one or more sets of states, perform a conquer step grouping of the states of the state table based on the second one or more sets of states and conquer criteria to generate third one or more sets of states, and generate a two dimensioned compressed state table based on the third one or more sets of states. The memory circuit is configured to store the two dimensioned compressed state table.

    Methods and apparatus for intelligent power reduction in communications systems

    公开(公告)号:US10862702B2

    公开(公告)日:2020-12-08

    申请号:US14695261

    申请日:2015-04-24

    Abstract: Methods and systems are provided for power control in communications devices. Bonding of channels in communication devices may be dynamically adjusted, such as responsive to requests for bandwidth adjustment. For example, bonded channel configurations may be adjusted based on power, such as to single channel configurations (or to channel configurations with small number of channels, such as relative to current configurations) for low power operations. Components (or functions thereof) used in conjunction with receiving and/or processing bonded channels may be dynamically adjusted. Such dynamic adjustments may be performed, for example, such as to maintain required synchronization and system information to facilitate rapid data transfer resumption upon demand.

    Digital-to-analog converter
    50.
    发明授权

    公开(公告)号:US10855300B2

    公开(公告)日:2020-12-01

    申请号:US16369276

    申请日:2019-03-29

    Abstract: A digital-to-analog converter is provided. The digital-to-analog converter includes a plurality of digital-to-analog converter cells coupled to an output node of the digital-to-analog converter. At least one of the plurality of digital-to-analog converter cells includes a capacitive element configured to generate an analog cell output signal based on a drive signal. The at least one of the plurality of digital-to-analog converter cells further includes a driver circuit configured to generate the drive signal, and a resistive element exhibiting a resistance of at least 20Ω. The resistive element is coupled between the driver circuit and the capacitive element or between the capacitive element and the output node.

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