公开(公告)号：US20040165452A1

公开(公告)日：2004-08-26

申请号：US10689062

申请日：2003-10-21

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Masaya Nakano

IPC: G11C007/00

CPC classification number: G11C29/12015 ,  G11C7/1078 ,  G11C7/109 ,  G11C11/401 ,  G11C29/14 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50016

Abstract: An internal RAS generating circuit generates an internal signal instructing activation of a word line, based on a control command received from the outside. The internal RAS generating circuit activates the internal signal at least during a period in which an internal RAS guarantee signal received from an internal RAS guarantee signal generating circuit is asserted, regardless of the control command instructing inactivation of the word line. In a normal operation mode, the internal RAS guarantee signal generating circuit activates the internal RAS guarantee signal until a prescribed period guaranteeing a restoring operation elapses, while in the test mode, it inactivates the internal RAS guarantee signal.

Abstract translation: 内部RAS生成电路基于从外部接收的控制命令，生成指示字线的激活的内部信号。 至少在从内部RAS保证信号发生电路接收到的内部RAS保证信号被断言的时段内，内部RAS产生电路激活内部信号，而不管指示字线失活的控制命令如何。 在正常工作模式下，内部RAS保证信号发生电路激活内部RAS保证信号，直到保证恢复运行的规定期间过去，而在测试模式下，内部RAS保证信号失效。

公开(公告)号：US20040164988A1

公开(公告)日：2004-08-26

申请号：US10669261

申请日：2003-09-25

Applicant: RENESAS TECHNOLOGY CORP. ,  RENESAS LSI DESIGN CORPORATION.

Inventor： Seiji Matsumoto

IPC: G06F013/00

CPC classification number: G09G5/003 ,  G09G2340/12

Abstract: An on-screen display unit includes OSD (on-screen display) RAMs each for storing data on one of OSD blocks to be subjected to OSD; a memory bus for transferring data to be stored to the OSD RAMs from a CPU; and an OSD local bus for transferring the data stored in the OSD RAMs to make the OSD. The OSD RAMs are supplied with the data to be stored through the control of switches alternately, and transfer the stored data to the OSD local bus 12 alternately. The on-screen display unit can cope with a high frequency OSD clock signal, and carry out the OSD normally.

Abstract translation: 屏幕显示单元包括OSD（屏幕显示）RAM，每个RAM用于存储要进行OSD的OSD块之一的数据; 用于从CPU传送要存储到OSD RAM的数据的存储器总线; 以及用于传送存储在OSD RAM中的数据以进行OSD的OSD本地总线。 交替地通过开关控制的OSD RAM来提供要存储的数据，并将存储的数据交替地传送到OSD本地总线12。 屏幕显示单元可以处理高频OSD时钟信号，并正常执行OSD。

公开(公告)号：US20040164428A1

公开(公告)日：2004-08-26

申请号：US10784276

申请日：2004-02-24

Applicant: Renesas Technology Corp. ,  Hitachi ULSI System Co., Ltd. ,  Hitachi Yonezawa Electronics Co., Ltd.

Inventor： Noriyuki Takahashi ,  Masayuki Suzuki ,  Kouji Tsuchiya ,  Takao Matsuura ,  Takanori Hashizume ,  Masahiro Ichitani ,  Kazunari Suzuki ,  Takafumi Nishita ,  Kenichi Imura ,  Takashi Miwa

IPC: H01L023/48

CPC classification number: H01L23/564 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20752 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/00012

Abstract: The back side of a strip substrate with plural semiconductor chips mounted thereon is vacuum-chucked to a lower mold half of a mold, and in this state the plural semiconductor chips are sealed with resin simultaneously to form a seal member. Thereafter, the strip substrate and the seal member are released from the mold and are cut into plural semiconductor devices. The semiconductor devices thus obtained are improved in their mounting reliability.

Abstract translation: 将其上安装有多个半导体芯片的带状基板的背面真空吸附到模具的下半模，并且在该状态下，多个半导体芯片同时用树脂密封以形成密封构件。 此后，带状基板和密封构件从模具中释放并切割成多个半导体器件。 由此获得的半导体器件的安装可靠性得到改善。

公开(公告)号：US20040163246A1

公开(公告)日：2004-08-26

申请号：US10717718

申请日：2003-11-21

Applicant: Renesas Technology Corp. ,  MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Yasutaka Nishioka ,  Junjiro Sakai ,  Shingo Tomohisa ,  Susumu Matsumoto ,  Fumio Iwamoto ,  Michinari Yamanaka

IPC: H05K003/10

CPC classification number: H01L21/76808 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: It is an object to provide a semiconductor device having a buried multilayer wiring structure in which generation of a resolution defect of a resist pattern is suppressed and generation of a defective wiring caused by the resolution defect is reduced. After a via hole (7) reaching an etching stopper film (4) is formed, annealing is carried out at 300 to 400null C. with the via hole (7) opened. As an annealing method, it is possible to use both a method using a hot plate and a method using a heat treating furnace. In order to suppress an influence on a lower wiring (20) which has been manufactured, heating is carried out for a short time of approximately 5 to 10 minutes by using the hot plate. Consequently, a by-product staying in an interface of an upper protective film (6) and an interlayer dielectric film (5) having a low dielectric constant and a by-product staying in an interface of the etching stopper film (4) and the interlayer dielectric film (5) having a low dielectric constant are discharged so that an amount of the residual by-product can be decreased.

Abstract translation: 本发明的目的是提供一种具有掩埋多层布线结构的半导体器件，其中抗蚀剂图案的分辨率缺陷的产生被抑制，并且由分辨率缺陷引起的缺陷布线的产生减少。 在形成到达蚀刻停止膜（4）的通孔（7）之后，在通孔（7）打开的情况下，在300〜400℃进行退火。 作为退火方法，可以使用使用热板的方法和使用热处理炉的方法。 为了抑制对制造的下布线（20）的影响，通过使用热板进行约5〜10分钟的短时间的加热。 因此，残留在上部保护膜（6）和具有低介电常数的副产物残留在蚀刻阻挡膜（4）的界面上的层间电介质膜（5）的界面中的副产物和 排出具有低介电常数的层间绝缘膜（5），从而可以减少残留副产物的量。

公开(公告)号：US20040162936A1

公开(公告)日：2004-08-19

申请号：US10611865

申请日：2003-07-03

Applicant: Renesas Technology Corp.

Inventor： Akiko Hisasue ,  Junji Tateishi

IPC: G06F013/28

CPC classification number: G06Q10/00

Abstract: A material control system which provides for centralized control of a stock and an order so as to keep an appropriate control of materials in stock without differentiating a material which requires a regenerating process and a material which does not require a regenerating process. The material control system includes a master table storing information for controlling each of materials. The information is provided in an entry field of a regeneration control flag (104) indicating whether or not each of materials to be used in a manufacturing apparatus is regeneratable and an entry field of a regeneration order control flag (201) indicating whether or not a registered contractor is a seller or a regeneration contractor. The material control system further includes an order control section for making a purchase order for the materials and an order for a regenerating process, using the regeneration order control flag (201), and a stock control section for controlling a stock of the materials. The order control section and the stock control section are controlled in a centralized manner.

Abstract translation: 一种材料控制系统，其提供对库存和订单的集中控制，以便在不需要再生过程的材料和不需要再生过程的材料的情况下保持库存中材料的适当控制。 材料控制系统包括存储用于控制每个材料的信息的主表。 该信息被提供在再现控制标志（104）的输入字段中，指示制造装置中要使用的每种材料是否可再生，再生指令控制标志（201）的输入字段是否指示 注册承办商是卖方或再生承包商。 材料控制系统还包括使用再生顺序控制标志（201）和用于控制材料的库存的库存控制部分进行材料的采购订单和再生处理的订单的订单控制部分。 以集中方式控制订单控制部和库存控制部。

公开(公告)号：US20040162932A1

公开(公告)日：2004-08-19

申请号：US10776962

申请日：2004-02-10

Applicant: Renesas Technology Corp.

Inventor： Nagamasa Mizushima ,  Motoyasu Tsunoda ,  Kunihiro Katayama

IPC: G06F012/14

CPC classification number: G07F7/1008 ,  G06F12/1458 ,  G06F21/77 ,  G06F21/78 ,  G06Q20/341 ,  G06Q20/3552 ,  G06Q20/3576

Abstract: In one aspect of the present invention, a memory device comprises an interface which interfaces with an external device, an IC chip which stores one or more application programs and executes the application programs, a memory which stores associated data associated with the one or more application programs, and a controller connected with the interface, the IC chip, and the memory. In response to a predetermined command received from the external device by way of the interface, the controller performs transfer of the associated data between the IC chip and the memory without passing the associated data to the host device during transfer of the associated data between the IC chip and the memory.

Abstract translation: 在本发明的一个方面，一种存储设备包括与外部设备接口的接口，存储一个或多个应用程序并执行应用程序的IC芯片，存储与一个或多个应用相关联的相关数据的存储器 程序，以及与接口连接的控制器，IC芯片和存储器。 响应于通过接口从外部设备接收到的预定命令，控制器在IC芯片和存储器之间执行传送相关联的数据，而不会在IC之间的相关数据传送期间将相关联的数据传送到主机设备 芯片和内存。

公开(公告)号：US20040160842A1

公开(公告)日：2004-08-19

申请号：US10654948

申请日：2003-09-05

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Takahiko Fukiage

IPC: G11C008/00

CPC classification number: G11C11/4091 ,  G11C7/06 ,  G11C8/12 ,  G11C8/18 ,  G11C2207/065

Abstract: In a semiconductor memory device including a plurality of memory chips, the plurality of memory chips are divided into first and second groups that are operated in parallel with each other at the time of a data read. Timings of activating sense amplifiers belonging to the first and second groups are made different from each other. Accordingly, the maximum value of peak current generated when the sense amplifiers are activated at the time of a data read is reduced by half in the semiconductor memory device as a whole. As the peak current is suppressed, the data reading operation can be executed stably.

公开(公告)号：US20040159866A1

公开(公告)日：2004-08-19

申请号：US10617665

申请日：2003-07-14

Applicant: Renesas Technology Corp.

Inventor： Kazuhiro Aihara

IPC: H01L029/76 ,  H01L031/062 ,  H01L031/119 ,  H01L031/117

CPC classification number: H01L21/2807 ,  H01L29/4966 ,  H01L29/78

Abstract: A source region (2) and a drain region (3) both containing n-type impurities are formed on a p-type Si semiconductor substrate (1) containing p-type impurities. On an active region of the surface of the p-type Si semiconductor substrate (1) between the source region (2) and the drain region (3), a gate insulating film (4) is formed. An n-type SiGe mixed crystal film (5) containing n-type impurities is formed on the gate insulating film (4) and a p-type SiGe mixed crystal film (6) containing p-type impurities is formed on the n-type SiGe mixed crystal film (5). A semiconductor device including such a transistor can further inhibit an increase in leakage current flowing between the gate electrode and the drain through the gate insulating film.

Abstract translation: 在包含p型杂质的p型Si半导体衬底（1）上形成都含有n型杂质的源区（2）和漏区（3）。 在源极区域（2）和漏极区域（3）之间的p型Si半导体衬底（1）的表面的有源区上形成栅极绝缘膜（4）。 在栅极绝缘膜（4）上形成含有n型杂质的n型SiGe混合晶体膜（5），在n型上形成含有p型杂质的p型SiGe混合晶体膜（6） SiGe混晶膜（5）。 包括这种晶体管的半导体器件可以进一步抑制通过栅极绝缘膜在栅电极和漏极之间流动的漏电流的增加。

公开(公告)号：US20040157465A1

公开(公告)日：2004-08-12

申请号：US10449128

申请日：2003-06-02

Applicant: Renesas Technology Corp.

Inventor： Kenji Kawai

IPC: H01L021/302

CPC classification number: H01L21/76802 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76826 ,  H01L21/76829

Abstract: A method for manufacturing an electronic device, in which a film of low dielectric constant is subjected to etching while a resist pattern formed on a substratenullon which the film of low dielectric constant is formednullis taken as a mask. Subsequently, the resist pattern is removed by ashing through use of ashing gas. After the ashing operation, an alteration layer formed on the film of low dielectric constant is removed. Alternatively, before ashing operation, a thin film for inhibiting penetration of oxygen is formed on the surface or side surfaces of the film of low dielectric constant. Further alternatively, gas which inhibits oxidization of the film of low dielectric constant is used as the ashing gas.

Abstract translation: 一种电子器件的制造方法，其中将低介电常数的膜进行蚀刻，同时形成在其上形成有低介电常数的膜的衬底上的抗蚀剂图案作为掩模。 随后，通过使用灰化气体通过灰化除去抗蚀剂图案。 在灰化操作之后，去除在低介电常数膜上形成的改变层。 或者，在灰化操作之前，在低介电常数的膜的表面或侧表面上形成用于抑制氧的渗透的薄膜。 另外，作为灰化气体，使用抑制低介电常数的膜的氧化的气体。

公开(公告)号：US20040157424A1

公开(公告)日：2004-08-12

申请号：US10603773

申请日：2003-06-26

Applicant: Renesas Technology Corp.

Inventor： Yoshihiro Kusumi ,  Takeru Matsuoka ,  Shoichi Fukui

IPC: H01L021/44

CPC classification number: H01L21/76886 ,  H01L21/76805 ,  H01L21/76838 ,  H01L23/5226 ,  H01L23/53219 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An AlCu alloy interconnect line (100) including a TiN barrier layer (110), a lower Ti metal layer (120), an AlCu layer (130) and a TiN cap layer (140) is formed on a plasma oxide film formed on a semiconductor substrate in which devices are formed. Heat treatment is conducted to cause Al contained in the AlCu layer (130) and Ti contained in the lower Ti metal layer (120) to react with each other, thereby forming a lower AlTi alloy layer (150) in a lower portion of the AlCu layer (130). A via hole (170) is thereafter formed. A current path extending from the via hole (170) to reach the lower AlTi alloy layer (150) is ensured without passing through the AlCu layer (130), allowing electromigration resistance to be improved.

Abstract translation: 在形成于其上的等离子体氧化膜上形成包括TiN阻挡层（110），下部Ti金属层（120），AlCu层（130）和TiN覆盖层（140）的AlCu合金布线（100） 形成器件的半导体衬底。 进行热处理以使AlCu层（130）中所含的Al和下部Ti金属层（120）中所含的Ti彼此反应，从而在AlCu的下部形成下部AlTi合金层（150） 层（130）。 之后形成通孔（170）。 确保从通孔（170）延伸到达下AlTi合金层（150）的电流路径，而不通过AlCu层（130），从而提高电迁移阻力。