FUSE CIRCUIT
    41.
    发明申请
    FUSE CIRCUIT 有权
    保险丝电路

    公开(公告)号:US20130147542A1

    公开(公告)日:2013-06-13

    申请号:US13570400

    申请日:2012-08-09

    Applicant: Sang Kwon LEE

    Inventor: Sang Kwon LEE

    CPC classification number: G11C17/16 G06F11/1048

    Abstract: A fuse circuit includes a programming fuse signal generation block configured to generate parity signals, logic levels of which are determined according to addresses selected among a plurality of addresses with a programming enable signal enabled, and generate programming fuse signals which are programmed in response to the programming enable signal, the plurality of addresses and the parity signals; a corrected pulse generation block configured to correct an error included in the programming fuse signals and generate corrected pulses; and a fuse unit configured to generate fuse signals which are reprogrammed according to the corrected pulses.

    Abstract translation: 熔丝电路包括编程熔丝信号产生块,其被配置为产生奇偶校验信号,其逻辑电平根据在多个地址中选择的地址而被确定,其中编程使能信号使能,并产生编程熔丝信号,其响应于 编程使能信号,多个地址和奇偶校验信号; 校正脉冲发生块,被配置为校正编程熔丝信号中包括的误差并产生校正脉冲; 以及熔丝单元,被配置为产生根据校正的脉冲重新编程的熔丝信号。

    System and method of providing quality of service-enabled contents in peer-to-peer networks
    42.
    发明授权
    System and method of providing quality of service-enabled contents in peer-to-peer networks 有权
    在对等网络中提供服务质量的内容的系统和方法

    公开(公告)号:US08335844B2

    公开(公告)日:2012-12-18

    申请号:US11872181

    申请日:2007-10-15

    Abstract: A system and method of providing quality of service (QoS)-enabled digital content in peer-to-peer (P2P) networks are provided. The QoS-enabled service system on the P2P network includes: a service provider capable of providing digital content; one or more user nodes receiving digital content from the service provider; one or more donor nodes lending resources for providing digital content; and a supernode receiving information on user nodes and donor nodes, and a copy of digital content from the service provider, allowing the exchange of digital content among the user nodes through P2P networking, and when at least one user node experiences a P2P networking error during the exchange of the digital content, arranging for a predetermined number of donor nodes from among the one or more donor nodes to join the P2P networking. According to the system and method, even when the function of a peer does not normally work on a P2P network, a donor as a replacement of the peer is utilized, thereby providing QoS-enabled digital content to a user requesting the digital content.

    Abstract translation: 提供了一种在对等(P2P)网络中提供服务质量(QoS)的数字内容的系统和方法。 P2P网络上支持QoS的业务系统包括:能够提供数字内容的业务提供者; 从服务提供商接收数字内容的一个或多个用户节点; 一个或多个捐赠节点为提供数字内容提供资源; 以及从用户节点和供体节点接收信息的超级节点,以及来自服务提供商的数字内容的副本,允许通过P2P网络在用户节点之间交换数字内容,并且当至少一个用户节点在P2P网络中经历P2P网络错误时 数字内容的交换,从一个或多个捐赠者节点安排预定数量的捐赠者节点以加入P2P网络。 根据该系统和方法,即使对等体的功能在P2P网络上不能正常工作,也可以利用作为对等体的替代者的供体,从而向请求数字内容的用户提供支持QoS的数字内容。

    SERVER FOR SINGLE SIGN ON, DEVICE ACCESSING SERVER AND CONTROL METHOD THEREOF
    43.
    发明申请
    SERVER FOR SINGLE SIGN ON, DEVICE ACCESSING SERVER AND CONTROL METHOD THEREOF 审中-公开
    用于单点登录的服务器,访问服务器的设备及其控制方法

    公开(公告)号:US20120131343A1

    公开(公告)日:2012-05-24

    申请号:US13240461

    申请日:2011-09-22

    CPC classification number: H04L63/0815

    Abstract: Disclosed are a server, a device accessing the server and a control method thereof, the server for single sign on including: a storage unit which stores user information of a second device; and a controller which identifies a second device which is accessed by a same user as a user of a first device and which stores account information, if the first device requests the account information for a content provider. With this configuration, there are provided a server which shares account information for a content provider, a device accessing the server and a control method thereof.

    Abstract translation: 公开了服务器,访问服务器的设备及其控制方法,用于单点登录的服务器包括:存储单元,其存储第二设备的用户信息; 以及控制器,其识别与第一设备的用户相同的用户访问并且存储帐户信息的第二设备,如果第一设备请求内容提供商的帐户信息。 利用该配置,提供了一种共享用于内容提供商的帐户信息,访问服务器的设备及其控制方法的服务器。

    Active cycle control circuit for semiconductor memory apparatus
    44.
    发明授权
    Active cycle control circuit for semiconductor memory apparatus 有权
    半导体存储装置的主动周期控制电路

    公开(公告)号:US08149641B2

    公开(公告)日:2012-04-03

    申请号:US12411613

    申请日:2009-03-26

    Applicant: Sang-Kwon Lee

    Inventor: Sang-Kwon Lee

    CPC classification number: G11C11/406 G11C7/1063 G11C2211/4067

    Abstract: An active cycle control circuit for a semiconductor memory apparatus is configured to precharge a word line corresponding to a read cycle, and activate a word line corresponding to a refresh request signal in response to the refresh request signal generated during the read cycle.

    Abstract translation: 半导体存储装置的有源周期控制电路被配置为对与读周期相对应的字线进行预充电,并且响应于在读周期期间产生的刷新请求信号,激活与刷新请求信号对应的字线。

    Refresh signal generating circuit
    45.
    发明授权
    Refresh signal generating circuit 有权
    刷新信号发生电路

    公开(公告)号:US08050128B2

    公开(公告)日:2011-11-01

    申请号:US13015344

    申请日:2011-01-27

    Applicant: Sang Kwon Lee

    Inventor: Sang Kwon Lee

    Abstract: A refresh signal generating circuit of a semiconductor memory device includes a flag signal generator which generates a flag signal in response to a refresh signal and a precharge signal, a clock enable signal buffer which generates first and second buffer enable signals based on an external clock enable signal in response to the flag signal, and a chip select signal buffer which generates an internal chip select signal based on an external chip select signal in response to the flag signal.

    Abstract translation: 半导体存储器件的刷新信号产生电路包括一个标志信号发生器,该标志信号发生器响应于刷新信号和一个预充电信号产生一个标志信号;一个时钟使能信号缓冲器,其基于外部时钟使能产生第一和第二缓冲器使能信号 响应于标志信号的信号,以及片选信号缓冲器,其响应于标志信号,基于外部片选信号产生内部片选信号。

    Refresh controlling circuit
    46.
    发明授权
    Refresh controlling circuit 有权
    刷新控制电路

    公开(公告)号:US07768858B2

    公开(公告)日:2010-08-03

    申请号:US12005478

    申请日:2007-12-27

    Applicant: Sang Kwon Lee

    Inventor: Sang Kwon Lee

    Abstract: A refresh controlling circuit includes an MRS latch unit configured to output a mask information signal of a bank and a mask information signal of a segment by synchronizing a first address signal and a second address signal with a pulse signal, a bank active control unit configured to output a bank active signal in response to the mask information signal of the bank, and a decoding unit configured to output a row address decoding signal in response to the bank active signal, the mask information signal of the segment, and a third address signal.

    Abstract translation: 刷新控制电路包括:MRS锁存单元,被配置为通过使第一地址信号和第二地址信号与脉冲信号同步来输出存储体的掩码信息信号和段的掩码信息信号;存储体活动控制单元,被配置为 响应于存储体的掩模信息信号输出存储体活动信号,以及解码单元,被配置为响应于存储体活动信号,区段的掩模信息信号和第三地址信号输出行地址解码信号。

    SYSTEM AND METHOD FOR SHOPPING
    47.
    发明申请
    SYSTEM AND METHOD FOR SHOPPING 审中-公开
    用于购物的系统和方法

    公开(公告)号:US20100153233A1

    公开(公告)日:2010-06-17

    申请号:US12531932

    申请日:2008-03-18

    Abstract: Provided are a system and method for shopping, and more particularly, a system and method for shopping, in which a display device transmits control authority to a content-providing device connected by a predetermined communication network, and the content-providing device receives the control authority, configures a screen, which includes at least a piece of content, according to the received control authority and the results of a service request, and provides the configured screen to the display device so that the configured screen can be displayed on the display device.

    Abstract translation: 本发明提供一种用于购物的系统和方法,更具体地说,一种用于购物的系统和方法,其中显示装置向由预定通信网络连接的内容提供设备发送控制权限,并且内容提供设备接收控制 授权,根据接收到的控制权限和服务请求的结果,配置至少包含一条内容的屏幕,并将配置的屏幕提供给显示设备,使得配置的屏幕可以显示在显示设备上 。

    Apparatus and method for controlling active cycle of semiconductor memory apparatus
    48.
    发明授权
    Apparatus and method for controlling active cycle of semiconductor memory apparatus 有权
    用于控制半导体存储装置的有效周期的装置和方法

    公开(公告)号:US07711969B2

    公开(公告)日:2010-05-04

    申请号:US11600156

    申请日:2006-11-16

    Applicant: Sang-Kwon Lee

    Inventor: Sang-Kwon Lee

    CPC classification number: G11C7/1045 G11C7/1072

    Abstract: An apparatus for controlling an active cycle of semiconductor memory that supports a synchronous mode and an asynchronous mode is provided. The apparatus includes an operational mode control unit that determines the operational mode of the semiconductor memory on the basis of a clock signal for a predetermined time and outputs an operational mode determination signal, and an active control unit that controls the output of an active signal for executing an active cycle of the corresponding operational mode on the basis of the operational mode determination signal.

    Abstract translation: 提供一种用于控制支持同步模式和异步模式的半导体存储器的有效周期的装置。 该装置包括操作模式控制单元,其基于时钟信号在预定时间内确定半导体存储器的操作模式并输出操作模式确定信号;以及主动控制单元,其控制用于 基于操作模式确定信号执行相应操作模式的活动周期。

    Refresh signal generating circuit
    49.
    发明申请
    Refresh signal generating circuit 有权
    刷新信号发生电路

    公开(公告)号:US20090323436A1

    公开(公告)日:2009-12-31

    申请号:US12313102

    申请日:2008-11-17

    Applicant: Sang Kwon Lee

    Inventor: Sang Kwon Lee

    Abstract: A refresh signal generating circuit of a semiconductor memory device includes a flag signal generator which generates a flag signal in response to a refresh signal and a precharge signal, a clock enable signal buffer which generates first and second buffer enable signals based on an external clock enable signal in response to the flag signal, and a chip select signal buffer which generates an internal chip select signal based on an external chip select signal in response to the flag signal.

    Abstract translation: 半导体存储器件的刷新信号产生电路包括一个标志信号发生器,该标志信号发生器响应于刷新信号和一个预充电信号产生一个标志信号;一个时钟使能信号缓冲器,其基于外部时钟使能产生第一和第二缓冲器使能信号 响应于标志信号的信号,以及片选信号缓冲器,其响应于标志信号,基于外部片选信号产生内部片选信号。

    Column path circuit
    50.
    发明授权
    Column path circuit 有权
    列路径电路

    公开(公告)号:US07626885B2

    公开(公告)日:2009-12-01

    申请号:US12190281

    申请日:2008-08-12

    Applicant: Sang Kwon Lee

    Inventor: Sang Kwon Lee

    Abstract: A column path circuit includes address transition detectors which detect level transition of page address signals, thereby outputting transition detection signals each having a predetermined enable period, respectively. A detection signal coupler logically operates on the transition detection signals respectively outputted from the address transition detectors, and outputs a signal representing the results of the logical operation. A ready signal generator outputs a strobe ready signal having a predetermined enable period in response to an enabled state of the signal outputted from the detection signal coupler. A strobe signal generator generates a read strobe signal and a page address strobe signal for latch of the page address signals in response to the strobe ready signal. Page address buffers are enabled by the page address strobe signal, and latch the page address signals, thereby buffering the page address signals, a page address decoder which decodes the buffered page address signals respectively outputted from the page address buffers. And, a column selection signal generator outputs column selection signals respectively corresponding to the decoded page address signals in response to the read strobe signal.

    Abstract translation: 列路径电路包括地址转换检测器,其检测寻呼地址信号的电平转换,从而分别输出具有预定使能周期的转移检测信号。 检测信号耦合器对从地址转换检测器分别输出的转移检测信号进行逻辑运算,并输出表示逻辑运算结果的信号。 就绪信号发生器响应于从检测信号耦合器输出的信号的使能状态而输出具有预定使能周期的选通准备信号。 选通信号发生器响应于选通准备就绪信号而产生读选通信号和页寻址选通信号,用于锁存页地址信号。 页面地址选通信号使能页面地址缓冲器,并锁存页面地址信号,从而缓冲页面地址信号,对从页面地址缓冲器分别输出的缓冲页面地址信号进行解码的页面地址解码器。 并且,列选择信号发生器响应于读选通信号输出分别对应于解码页地址信号的列选择信号。

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