Abstract:
A fuse circuit includes a programming fuse signal generation block configured to generate parity signals, logic levels of which are determined according to addresses selected among a plurality of addresses with a programming enable signal enabled, and generate programming fuse signals which are programmed in response to the programming enable signal, the plurality of addresses and the parity signals; a corrected pulse generation block configured to correct an error included in the programming fuse signals and generate corrected pulses; and a fuse unit configured to generate fuse signals which are reprogrammed according to the corrected pulses.
Abstract:
A system and method of providing quality of service (QoS)-enabled digital content in peer-to-peer (P2P) networks are provided. The QoS-enabled service system on the P2P network includes: a service provider capable of providing digital content; one or more user nodes receiving digital content from the service provider; one or more donor nodes lending resources for providing digital content; and a supernode receiving information on user nodes and donor nodes, and a copy of digital content from the service provider, allowing the exchange of digital content among the user nodes through P2P networking, and when at least one user node experiences a P2P networking error during the exchange of the digital content, arranging for a predetermined number of donor nodes from among the one or more donor nodes to join the P2P networking. According to the system and method, even when the function of a peer does not normally work on a P2P network, a donor as a replacement of the peer is utilized, thereby providing QoS-enabled digital content to a user requesting the digital content.
Abstract:
Disclosed are a server, a device accessing the server and a control method thereof, the server for single sign on including: a storage unit which stores user information of a second device; and a controller which identifies a second device which is accessed by a same user as a user of a first device and which stores account information, if the first device requests the account information for a content provider. With this configuration, there are provided a server which shares account information for a content provider, a device accessing the server and a control method thereof.
Abstract:
An active cycle control circuit for a semiconductor memory apparatus is configured to precharge a word line corresponding to a read cycle, and activate a word line corresponding to a refresh request signal in response to the refresh request signal generated during the read cycle.
Abstract:
A refresh signal generating circuit of a semiconductor memory device includes a flag signal generator which generates a flag signal in response to a refresh signal and a precharge signal, a clock enable signal buffer which generates first and second buffer enable signals based on an external clock enable signal in response to the flag signal, and a chip select signal buffer which generates an internal chip select signal based on an external chip select signal in response to the flag signal.
Abstract:
A refresh controlling circuit includes an MRS latch unit configured to output a mask information signal of a bank and a mask information signal of a segment by synchronizing a first address signal and a second address signal with a pulse signal, a bank active control unit configured to output a bank active signal in response to the mask information signal of the bank, and a decoding unit configured to output a row address decoding signal in response to the bank active signal, the mask information signal of the segment, and a third address signal.
Abstract:
Provided are a system and method for shopping, and more particularly, a system and method for shopping, in which a display device transmits control authority to a content-providing device connected by a predetermined communication network, and the content-providing device receives the control authority, configures a screen, which includes at least a piece of content, according to the received control authority and the results of a service request, and provides the configured screen to the display device so that the configured screen can be displayed on the display device.
Abstract:
An apparatus for controlling an active cycle of semiconductor memory that supports a synchronous mode and an asynchronous mode is provided. The apparatus includes an operational mode control unit that determines the operational mode of the semiconductor memory on the basis of a clock signal for a predetermined time and outputs an operational mode determination signal, and an active control unit that controls the output of an active signal for executing an active cycle of the corresponding operational mode on the basis of the operational mode determination signal.
Abstract:
A refresh signal generating circuit of a semiconductor memory device includes a flag signal generator which generates a flag signal in response to a refresh signal and a precharge signal, a clock enable signal buffer which generates first and second buffer enable signals based on an external clock enable signal in response to the flag signal, and a chip select signal buffer which generates an internal chip select signal based on an external chip select signal in response to the flag signal.
Abstract:
A column path circuit includes address transition detectors which detect level transition of page address signals, thereby outputting transition detection signals each having a predetermined enable period, respectively. A detection signal coupler logically operates on the transition detection signals respectively outputted from the address transition detectors, and outputs a signal representing the results of the logical operation. A ready signal generator outputs a strobe ready signal having a predetermined enable period in response to an enabled state of the signal outputted from the detection signal coupler. A strobe signal generator generates a read strobe signal and a page address strobe signal for latch of the page address signals in response to the strobe ready signal. Page address buffers are enabled by the page address strobe signal, and latch the page address signals, thereby buffering the page address signals, a page address decoder which decodes the buffered page address signals respectively outputted from the page address buffers. And, a column selection signal generator outputs column selection signals respectively corresponding to the decoded page address signals in response to the read strobe signal.