公开(公告)号：US07297901B2

公开(公告)日：2007-11-20

申请号：US10579619

申请日：2004-11-11

Applicant: Sung-Young Lee

Inventor： Sung-Young Lee

IPC: B60L1/02

CPC classification number: B60H1/2225 ,  B60H2001/2268 ,  F24H3/0405 ,  F24H3/0429 ,  F24H3/0435 ,  F24H3/047 ,  F24H9/1872 ,  H05B3/14 ,  H05B3/50 ,  H05B2203/02

Abstract: Disclosed is a pre-heater for vehicles comprising: A PTC element module including a positive terminal composed of two sheets, an upper sheet of which has a fastening hole and upward bended ribs formed at opposite edges of the fastening hole; a ring-shaped insert insulator inserted between the ribs; a PTC element inserted into an inside of the insert insulator, a bottom surface of which is in contact with a lower sheet of the positive terminal; one heat fin assembly closely fastened to one surface of the PTC element; another heat fin assembly fastened to the other surface of the PTC element through the medium of a positive terminal and an entire surface insulator; and a fastening insulator for binding together the two heat fin assemblies, the PTC element, the positive terminal and the entire surface insulator, and a heat fin assembly disposed parallel to the PTC element module; a negative terminal disposed parallel to the heat fin assembly; frames and respectively fastened to both ends of a combined body including the PTC element module; the heat fin assembly, and the negative terminal; and housing and respectively fastened to both longitudinal ends of a combined body including the PTC element module, the heat fin assembly, the negative terminal, and the frames and. In accordance with the present invention, the pre-heater has advantages capable of more facilitating assembly and maintenance and remarkably improving productivity, since the PTC element module and so on may be modulized.

Abstract translation: 公开了一种用于车辆的预热器，包括：PTC元件模块，包括由两片构成的正极端子，其上片具有形成在所述紧固孔的相对边缘处的紧固孔和向上弯曲的肋; 插入肋之间的环形插入绝缘体; PTC元件插入插入式绝缘子的内部，其底面与正端子的下片接触; 紧固在PTC元件的一个表面上的一个散热片组件; 通过正端子和整个表面绝缘体的介质固定到PTC元件的另一表面的另一个散热片组件; 以及用于将两个散热片组件，PTC元件，正极端子和整个表面绝缘体结合在一起的紧固绝缘体，以及平行于PTC元件模块设置的散热片组件; 平行于散热片组件布置的负极端子; 并且分别固定在包括PTC元件模块的组合主体的两端; 散热片组件和负极端子; 和壳体，并且分别固定到包括PTC元件模块，散热片组件，负极端子和框架的组合主体的两个纵向端部。 根据本发明，由于可以对PTC元件模块等进行模块化，所以预热器具有能够更方便组装和维护并显着提高生产率的优点。

公开(公告)号：US07265031B2

公开(公告)日：2007-09-04

申请号：US10972972

申请日：2004-10-25

Applicant: Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

Inventor： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

IPC: H01L21/84

CPC classification number: H01L29/785 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/78603

Abstract: An SOI substrate is fabricated by providing a substrate having a sacrificial layer thereon, an active semiconductor layer on the sacrificial layer remote from the substrate and a supporting layer that extends along at least two sides of the active semiconductor layer and the sacrificial layer and onto the substrate, and that exposes at least one side of the sacrificial layer. At least some of the sacrificial layer is etched through the at least one side thereof that is exposed by the supporting layer to form a void space between the substrate and the active semiconductor layer, such that the active semiconductor layer is supported in spaced-apart relation from the substrate by the supporting layer. The void space may be at least partially filled with an insulator lining.

Abstract translation: 通过在其上提供具有牺牲层的衬底，在远离衬底的牺牲层上的有源半导体层和沿着有源半导体层和牺牲层的至少两侧延伸的支撑层来制造SOI衬底 衬底，并且暴露出牺牲层的至少一侧。 牺牲层中的至少一部分被蚀刻穿过其至少一侧，其被支撑层暴露以在衬底和有源半导体层之间形成空隙，使得有源半导体层以间隔的关系支撑 通过支撑层从衬底。 空隙空间可以至少部分地填充有绝缘体衬里。

公开(公告)号：US07187022B2

公开(公告)日：2007-03-06

申请号：US11285300

申请日：2005-11-23

Applicant: Eun-jung Yun ,  Sung-min Kim ,  Sung-young Lee

Inventor： Eun-jung Yun ,  Sung-min Kim ,  Sung-young Lee

IPC: H01L29/80

CPC classification number: H01L29/66795 ,  H01L29/785

Abstract: In a semiconductor device having a multi-bridge-channel, and a method for fabricating the same, the device includes first and second semiconductor posts protruding from a surface of a semiconductor substrate and having a source and a drain region, respectively, in upper side portions thereof, channel semiconductor layers connecting upper side portions of the first and second semiconductor posts, a gate insulation layer on the channel semiconductor layers and the semiconductor substrate, the gate insulation layer surrounding at least a portion of the channel semiconductor layers, a gate electrode layer on the gate insulation layer to enclose at least a portion of a region between the channel semiconductor layers, and junction auxiliary layers formed between the channel semiconductor layers, the junction auxiliary layers contacting the gate electrode layer and upper side portions of the first and second semiconductor posts, and having a same width as the channel semiconductor layers.

Abstract translation: 在具有多桥通道的半导体器件及其制造方法中，该器件包括从半导体衬底的表面突出并分别具有源极和漏极区域的第一和第二半导体柱， 其部分，连接第一和第二半导体柱的上侧部分的沟道半导体层，沟道半导体层和半导体衬底上的栅极绝缘层，围绕至少一部分沟道半导体层的栅极绝缘层，栅电极 在所述栅绝缘层上包围所述沟道半导体层之间的区域的至少一部分，以及形成在所述沟道半导体层之间的接合辅助层，与所述栅电极层接触的所述结辅助层和所述第一和第二栅极的上侧部分 半导体柱，并且具有与沟道半导体层相同的宽度。

公开(公告)号：US20070045274A1

公开(公告)日：2007-03-01

申请号：US10579840

申请日：2004-08-03

Applicant: Sung-Young Lee

Inventor： Sung-Young Lee

IPC: A45D2/36 ,  A45D1/04 ,  A45D4/12 ,  A45D4/06

CPC classification number: F24H3/0429 ,  F24H3/0405 ,  F24H3/0435 ,  F24H3/0447 ,  F24H3/047 ,  F24H9/1872 ,  H05B3/14 ,  H05B3/50 ,  H05B2203/02

Abstract: Disclosed is a pre-heater for vehicles comprising: A PTC element module including a positive terminal composed of two sheets, an upper sheet of which has a fastening hole and upward bended ribs formed at opposite edges of the fastening hole; a ring-shaped insert insulator inserted between the ribs; a PTC element inserted into an inside of the insert insulator, a bottom surface of which is in contact with a lower sheet of the positive terminal; one heat fin assembly closely fastened to one surface of the PTC element; another heat fin assembly fastened to the other surface of the PTC element through the medium of a positive terminal and an entire surface insulator; and a fastening insulator for binding together the two heat fin assemblies, the PTC element, the positive terminal and the entire surface insulator, and a heat fin assembly disposed parallel to the PTC element module; a negative terminal disposed parallel to the heat fin assembly; frames and respectively fastened to both ends of a combined body including the PTC element module; the heat fin assembly, and the negative terminal; and housing and respectively fastened to both longitudinal ends of a combined body including the PTC element module, the heat fin assembly, the negative terminal, and the frames and. In accordance with the present invention, the pre-heater has advantages capable of more facilitating assembly and maintenance and remarkably improving productivity, since the PTC element module and so on may be modulized.

Abstract translation: 公开了一种用于车辆的预热器，包括：PTC元件模块，包括由两片构成的正极端子，其上片具有形成在所述紧固孔的相对边缘处的紧固孔和向上弯曲的肋; 插入肋之间的环形插入绝缘体; PTC元件插入插入式绝缘子的内部，其底面与正端子的下片接触; 紧固在PTC元件的一个表面上的一个散热片组件; 通过正端子和整个表面绝缘体的介质固定到PTC元件的另一表面的另一个散热片组件; 以及用于将两个散热片组件，PTC元件，正极端子和整个表面绝缘体结合在一起的紧固绝缘体，以及平行于PTC元件模块设置的散热片组件; 平行于散热片组件布置的负极端子; 并且分别固定在包括PTC元件模块的组合主体的两端; 散热片组件和负极端子; 和壳体，并且分别固定到包括PTC元件模块，散热片组件，负极端子和框架的组合主体的两个纵向端部。 根据本发明，由于可以对PTC元件模块等进行模块化，所以预热器具有能够更方便组装和维护并显着提高生产率的优点。

公开(公告)号：US20070034973A1

公开(公告)日：2007-02-15

申请号：US11461825

申请日：2006-08-02

Applicant: Eun-jung Yun ,  Sung-young Lee ,  Sung-min Kim ,  Dong-gun Park ,  Dong-uk Choi

Inventor： Eun-jung Yun ,  Sung-young Lee ,  Sung-min Kim ,  Dong-gun Park ,  Dong-uk Choi

IPC: H01L29/76

CPC classification number: H01L29/785 ,  H01L29/42392 ,  H01L29/7851 ,  H01L29/78612

Abstract: Some embodiments of the present invention provide methods and apparatus for operating a transistor including at least one fully depleted channel region in and/or on a substrate. The methods include applying a reverse body bias to the substrate when turning on the transistor. The substrate may be a bulk wafer substrate. The reverse body bias may allow the transistor to turn on while preventing turn on of a parasitic transistor in the substrate.

Abstract translation: 本发明的一些实施例提供了用于操作晶体管的方法和装置，所述晶体管包括在衬底中和/或衬底上的至少一个完全耗尽的沟道区。 所述方法包括在接通晶体管时将反体偏置施加到衬底。 衬底可以是体晶片衬底。 反向偏置可以允许晶体管导通，同时防止衬底中的寄生晶体管的导通。

公开(公告)号：US20060289907A1

公开(公告)日：2006-12-28

申请号：US11513474

申请日：2006-08-31

Applicant: Sung-Min Kim ,  Dong-Gun Park ,  Sung-Young Lee ,  Hye-Jin Cho ,  Eun-Jung Yun ,  Shin-Ae Lee ,  Chang-Woo Oh ,  Jeong-Dong Choe

Inventor： Sung-Min Kim ,  Dong-Gun Park ,  Sung-Young Lee ,  Hye-Jin Cho ,  Eun-Jung Yun ,  Shin-Ae Lee ,  Chang-Woo Oh ,  Jeong-Dong Choe

IPC: H01L29/76 ,  H01L21/8234

CPC classification number: H01L29/66651 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823487 ,  H01L29/0653

Abstract: A unit cell of a metal oxide semiconductor (MOS) transistor is provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate. The gate is between the source region and the drain region. First and second spaced apart buffer regions are provided beneath the source region and the drain region and between respective ones of the source region and integrated circuit substrate and the drain region and the integrated circuit substrate.

Abstract translation: 在集成电路基板上设置有集成电路基板和MOS晶体管的金属氧化物半导体（MOS）晶体管的单位电池。 MOS晶体管具有源极区，漏极区和栅极。 栅极在源极区域和漏极区域之间。 第一和第二间隔开的缓冲区设置在源极区域和漏极区域之间以及源区域和集成电路衬底以及漏极区域和集成电路衬底中的相应区域之间。

公开(公告)号：US20060240622A1

公开(公告)日：2006-10-26

申请号：US11407607

申请日：2006-04-20

Applicant: Sung-young Lee ,  Eun-jung Yun

Inventor： Sung-young Lee ,  Eun-jung Yun

IPC: H01L21/336

CPC classification number: H01L29/785 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78645

Abstract: Provided are a multi-channel semiconductor device and a method for manufacturing the semiconductor device through a simplified process. A sacrificial layer and a channel layer are alternately stacked on a semiconductor substrate. Thereafter, the sacrificial layer and the channel layer are etched to form a separated active pattern, and a device isolation layer is formed to cover sidewalls of the active pattern. Dopant ions are implanted into the entire semiconductor substrate, thereby forming a channel separation region under the active pattern. A portion of the active pattern is etched to separate the active pattern from a pair of facing sidewalls of the device separation layer, thereby forming a channel pattern having a pair of first exposed sidewalls. Source/drain semiconductor layers are formed on the first sidewalls of the channel pattern, and a part of the device isolation layer is removed to expose a pair of second sidewalls of the channel pattern contacting with the device separation layer. Thereafter, the sacrificial layer included in the channel pattern is remove, and a conductive layer for a gate electrode is formed to cover the channel layer exposed by the removing of the sacrificial layer.

Abstract translation: 提供了一种多通道半导体器件和通过简化工艺制造半导体器件的方法。 牺牲层和沟道层交替堆叠在半导体衬底上。 此后，蚀刻牺牲层和沟道层以形成分离的有源图案，并且形成器件隔离层以覆盖活性图案的侧壁。 将掺杂离子注入到整个半导体衬底中，从而在活性图案下形成沟道分离区。 蚀刻有源图案的一部分以将活性图案与器件分离层的一对相对的侧壁分离，从而形成具有一对第一暴露侧壁的沟道图案。 源极/漏极半导体层形成在沟道图案的第一侧壁上，并且去除器件隔离层的一部分以暴露与器件分离层接触的沟道图案的一对第二侧壁。 此后，去除包括在沟道图案中的牺牲层，并且形成用于栅电极的导电层以覆盖通过去除牺牲层而暴露的沟道层。

公开(公告)号：US07037768B2

公开(公告)日：2006-05-02

申请号：US10884749

申请日：2004-07-02

Applicant: Eun-jung Yun ,  Sung-young Lee ,  Chang-sub Lee ,  Sung-min Kim ,  Dong-gun Park

Inventor： Eun-jung Yun ,  Sung-young Lee ,  Chang-sub Lee ,  Sung-min Kim ,  Dong-gun Park

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/76

CPC classification number: H01L21/30604

Abstract: An integrated circuit device structure can be formed by forming an implant mask having a window therein on a structure including upper and lower Si layers and an intermediate SiGex layer therebetween. Ions are implanted through the upper Si layer and into a portion of the intermediate SiGex layer exposed through the window in the implant mask and blocking implantation of ions into portions of the intermediate SiGex layer outside the window. The portions of the intermediate SiGex layer outside the window are etched and the portion of the intermediate SiGex layer exposed through the window having ions implanted therein is not substantially etched to form a patterned intermediate SiGex layer.

Abstract translation: 集成电路器件结构可以通过在其上形成具有窗口的植入掩模形成在包括上和下Si层的结构和其间的中间SiGe x层之间形成。 离子通过上部Si层进入植入掩模中通过窗口暴露的中间SiGe层的一部分，并将离子注入到中间SiGe x x的部分中， SUB>层外面的窗口。 蚀刻窗口外部的中间SiGe x X层的部分，并且通过其中注入离子的窗口露出的中间SiGe层的部分基本上不被蚀刻以形成 图案化的中间SiGe x层。

公开(公告)号：US20060024874A1

公开(公告)日：2006-02-02

申请号：US11190695

申请日：2005-07-26

Applicant: Eun-jung Yun ,  Sung-min Kim ,  Sung-young Lee

Inventor： Eun-jung Yun ,  Sung-min Kim ,  Sung-young Lee

IPC: H01L21/336

CPC classification number: H01L29/78696 ,  H01L29/42392 ,  H01L29/66772

Abstract: A multi-bridge-channel MOSFET (MBCFET) may be formed by forming a stacked structure on a substrate that includes channel layers and interchannel layers interposed between the channel layers. Trenches are formed by selectively etching the stacked structure. The trenches run across the stacked structure parallel to each other and separate a first stacked portion including channel patterns and interchannel patterns from second stacked portions including channel and interchannel layers remaining on both sides of the first stacked portion. First source and drain regions are grown using selective epitaxial growth. The first source and drain regions fill the trenches and connect to second source and drain regions defined by the second stacked portions. Marginal sections of the interchannel patterns of the first stacked portion are selectively exposed. Through tunnels are formed by selectively removing the interchannel patterns of the first stacked portion beginning with the exposed marginal sections. The through tunnels are surrounded by the first source and drain regions and the channel patterns. A gate is formed along with a gate dielectric layer, the gate filling the through tunnels and extending onto the first stacked portion.

Abstract translation: 可以通过在包括沟道层和介于沟道层之间的沟道间层的衬底上形成层叠结构来形成多桥沟MOSFET（MBCFET）。 通过选择性地蚀刻堆叠结构形成沟槽。 沟槽横跨层叠结构彼此平行地延伸，并且将包括通道图案和沟道间图案的第一堆叠部分与第二堆叠部分分开，包括残留在第一堆叠部分两侧的通道和通道间层。 使用选择性外延生长生长第一源区和漏区。 第一源极和漏极区域填充沟槽并连接到由第二堆叠部分限定的第二源极和漏极区域。 选择性地暴露第一堆叠部分的通道间图案的边缘部分。 通过从暴露的边缘部分开始选择性地去除第一堆叠部分的通道间图案，形成通道。 穿通隧道被第一源极和漏极区域以及沟道图案包围。 栅极与栅极电介质层一起形成，栅极填充通孔并延伸到第一堆叠部分上。

公开(公告)号：US20050186742A1

公开(公告)日：2005-08-25

申请号：US11065002

申请日：2005-02-24

Applicant: Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Dong-Won Kim

Inventor： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Dong-Won Kim

IPC: H01L21/336 ,  H01L29/76 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L29/785 ,  H01L29/66818 ,  H01L29/78618

Abstract: A fin field-effect transistor (FinFET) device includes a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate. A gate electrode is formed on an upper surface and sidewalls of the channel region. First and second source/drain contacts are formed on respective upper surfaces and sidewalls of the first and second source/drain regions of the fin-shaped active region at opposite sides of the gate electrode. The channel region may be narrower than the first and second source/drain regions of the fin-shaped active region.

Abstract translation: 翅片场效应晶体管（FinFET）器件包括其中具有第一和第二源极/漏极区域的鳍状有源区域以及从半导体衬底垂直突出的沟道区域。 栅电极形成在沟道区的上表面和侧壁上。 第一和第二源极/漏极触点形成在栅极电极的相对侧的鳍状有源区域的第一和第二源极/漏极区域的相应上表面和侧壁上。 沟道区域可以比鳍状有源区域的第一和第二源极/漏极区域窄。