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公开(公告)号：US20060040567A1
公开(公告)日：2006-02-23
申请号：US10711076
申请日：2004-08-20
Applicant: William Bernier , Tien-Jen Cheng , Marie Cole , David Eichstadt , Mukta Farooq , John Fitzsimmons , Lewis Goldmann , John Knickerbocker , Tasha Lopez , David Welsh
Inventor： William Bernier , Tien-Jen Cheng , Marie Cole , David Eichstadt , Mukta Farooq , John Fitzsimmons , Lewis Goldmann , John Knickerbocker , Tasha Lopez , David Welsh
CPC classification number: H01L21/563 , H01L23/3171 , H01L24/12 , H01L24/16 , H01L24/81 , H01L2224/10126 , H01L2224/13099 , H01L2224/131 , H01L2224/13566 , H01L2224/16 , H01L2224/73203 , H01L2224/8121 , H01L2224/81815 , H01L2924/00011 , H01L2924/00013 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01R43/0256 , H05K3/284 , H05K3/3436 , H05K2201/0133 , H05K2201/10977 , Y02P70/613 , H01L2224/29099 , H01L2224/0401
Abstract: Disclosed is a method of forming an integrated circuit structure that forms lead-free connectors on a device, surrounds the lead-free connectors with a compressible film, connects the device to a carrier (the lead-free connectors electrically connect the device to the carrier), and fills the gaps between the carrier and the device with an insulating underfill.
Abstract translation: 公开了一种形成集成电路结构的方法，其在器件上形成无铅连接器，用可压缩膜围绕无铅连接器，将器件连接到载体（无铅连接器将器件电连接到载体上 ），并用绝缘底部填充物填充载体和装置之间的间隙。
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公开(公告)号：US20050167837A1
公开(公告)日：2005-08-04
申请号：US10707892
申请日：2004-01-21
Applicant: Tien-Jen Cheng , David Eichstadt , Jonathan Griffith , Sarah Knickerbocker , Samuel McKnight , Kevin Petrarca , Kamalesh Srivastava , Roger Quon
Inventor： Tien-Jen Cheng , David Eichstadt , Jonathan Griffith , Sarah Knickerbocker , Samuel McKnight , Kevin Petrarca , Kamalesh Srivastava , Roger Quon
IPC: H01L23/485 , H01L23/58 , H01L29/40
CPC classification number: H01L22/32 , H01L24/05 , H01L2224/0401 , H01L2224/05147 , H01L2224/05155 , H01L2224/05655 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14
Abstract: A durable chip pad for integrated circuit (IC) chips, semiconductor wafer with IC chips with durable chip pads in a number of die locations and a method of making the IC chips on the wafer. The chip may be probed for performance testing with the probe contacting the durable chip pads directly.
Abstract translation: 用于集成电路（IC）芯片的耐用芯片焊盘，具有在多个芯片位置具有耐用芯片焊盘的IC芯片的半导体晶片以及在晶片上制造IC芯片的方法。 可以通过探头直接接触耐用的芯片焊盘来探测芯片进行性能测试。
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43.发明申请公开(公告)号：US20050104208A1
公开(公告)日：2005-05-19
申请号：US10707021
申请日：2003-11-14
Applicant: James Bartelo , Tien-Jen Cheng , David Eichstadt , Charles Goldsmith , Jonathan Griffith , Donald Henderson , Roger Quon , Stephen Kilpatrick
Inventor： James Bartelo , Tien-Jen Cheng , David Eichstadt , Charles Goldsmith , Jonathan Griffith , Donald Henderson , Roger Quon , Stephen Kilpatrick
IPC: H01L23/485 , H01L23/48
CPC classification number: H01L24/10 , H01L24/13 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05181 , H01L2224/05647 , H01L2224/13 , H01L2224/13099 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , H01L2924/00 , H01L2924/00014 , H01L2924/013
Abstract: Disclosed is an improved integrated circuit structure that has internal circuitry and interconnects (e.g. C4, etc.) on an external portion of the structure. With the invention, these interconnects have a metal layer on the external portion of the structure, a first copper layer on the metal layer, a barrier layer on the copper layer, a stabilizing copper layer on the barrier layer, and a tin-based solder bump on the barrier layer. The stabilizing copper layer has a sufficient amount of copper to balance the chemical potential gradient of copper across the barrier layer and prevent copper within the first copper layer from diffusing across the barrier layer. Alternatively, a sufficient amount of copper can be included within the tin-based solder bump to prevent copper from diffusing across the barrier layer. Thus, the tin-based solder bump comprises a copper rich solder alloy.
Abstract translation: 公开了一种改进的集成电路结构，其在该结构的外部部分上具有内部电路和互连（例如C4等）。 通过本发明，这些互连在结构的外部具有金属层，金属层上的第一铜层，铜层上的阻挡层，阻挡层上的稳定铜层和锡基焊料 在阻挡层上碰撞。 稳定铜层具有足够量的铜以平衡横跨阻挡层的铜的化学势梯度，并防止第一铜层内的铜扩散穿过势垒层。 或者，可以在锡基焊料凸块内包含足够量的铜，以防止铜在阻挡层上扩散。 因此，锡基焊料凸块包括富含铜的焊料合金。
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公开(公告)号：US20050026416A1
公开(公告)日：2005-02-03
申请号：US10604578
申请日：2003-07-31
Applicant: Tien-Jen Cheng , David Eichstadt , Jonathan Griffith , Randolph Knarr , Kevin Petrarca , Roger Quon
Inventor： Tien-Jen Cheng , David Eichstadt , Jonathan Griffith , Randolph Knarr , Kevin Petrarca , Roger Quon
CPC classification number: H01L24/11 , H01L24/13 , H01L2224/03622 , H01L2224/05001 , H01L2224/05026 , H01L2224/05568 , H01L2224/05647 , H01L2224/1147 , H01L2224/11849 , H01L2224/13076 , H01L2224/13099 , H01L2224/131 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , H05K3/3457 , H05K3/4007 , H01L2224/05099
Abstract: A solder bump for bonding an electronic device to a substrate or another structure is formed by plating a high aspect ratio copper pin on a supporting structure, encapsulating the pin in a barrier material, plating a solder on the barrier material and then reflowing the solder.
Abstract translation: 通过在支撑结构上镀覆高纵横比的铜针，将该引脚封装在阻挡材料中，将焊料电镀在阻挡材料上，然后回流焊料，形成用于将电子器件接合到衬底或其它结构的焊料凸块。
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