公开(公告)号：US08716069B2

公开(公告)日：2014-05-06

申请号：US13631471

申请日：2012-09-28

Applicant: Yan Xun Xue ,  Yueh-Se Ho ,  Yongping Ding

Inventor： Yan Xun Xue ,  Yueh-Se Ho ,  Yongping Ding

IPC: H01L21/00 ,  H01R43/00 ,  H01L23/495 ,  H05K5/02

CPC classification number: H01L23/49861 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3171 ,  H01L23/36 ,  H01L23/49503 ,  H01L23/49562 ,  H01L23/49579 ,  H01L24/97 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  Y10T29/49121 ,  Y10T29/49172 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device comprises an aluminum alloy lead-frame with a passivation layer covering an exposed portion of the aluminum alloy lead-frame. Since aluminum alloy is a low-cost material, and its hardness and flexibility are suitable for deformation process, such as punching, bending, molding and the like, aluminum alloy lead frame is suitable for mass production; furthermore, since its weight is much lower than copper or iron-nickel material, aluminum alloy lead frame is very convenient for the production of semiconductor devices.

Abstract translation: 半导体器件包括具有覆盖铝合金引线框架的暴露部分的钝化层的铝合金引线框架。 由于铝合金是低成本材料，其硬度和柔韧性适用于冲压，弯曲，成型等变形过程，铝合金引线框架适合批量生产; 此外，由于其重量比铜或铁镍材料低得多，因此铝合金引线框对于半导体器件的生产非常方便。

公开(公告)号：US20130210215A1

公开(公告)日：2013-08-15

申请号：US13396531

申请日：2012-02-14

Applicant: Yan Xun Xue ,  Ping Huang ,  Yueh-Se Ho

Inventor： Yan Xun Xue ,  Ping Huang ,  Yueh-Se Ho

IPC: H01L21/78

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3114 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/94 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00015

Abstract: A packaging method with backside wafer dicing includes the steps of forming a support structure at the front surface of the wafer then depositing a metal layer on a centre area of the backside of the wafer after grinding the wafer backside to reduce the wafer thickness; detecting from the backside of the wafer sections of scribe lines formed in the front surface in the region between the edge of the metal layer and the edge of the wafer and cutting the wafer and the metal layer from the wafer backside along a straight line formed by extending a scribe line section detected from the wafer backside.

Abstract translation: 具有背面晶片切割的封装方法包括以下步骤：在晶片的前表面形成支撑结构，然后在晶片背面研磨之后在晶片背面的中心区域沉积金属层以减小晶片厚度; 从形成在金属层的边缘与晶片边缘之间的区域中的前表面的划线的背面检测，并从晶片背面沿着直线形成的直线切割晶片和金属层， 延伸从晶片背面检测的划线部分。

公开(公告)号：US20130134502A1

公开(公告)日：2013-05-30

申请号：US13750944

申请日：2013-01-25

Applicant: Yueh-Se Ho ,  Yan Xun Xue

Inventor： Yueh-Se Ho ,  Yan Xun Xue

IPC: H01L23/485 ,  H01L21/768

CPC classification number: H01L23/485 ,  H01L21/768 ,  H01L23/3114 ,  H01L23/4824 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/41741 ,  H01L29/42372 ,  H01L29/7802 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/06182 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/03 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor device, a method of manufacturing semiconductor devices and a circuit package assembly are described. A semiconductor device can have a semiconductor substrate with first and second surfaces and a sidewall between them. First and second conductive pads on the first and second surfaces are in electrical contact with corresponding first and second semiconductor device structures in the substrate. An insulator layer on the first surface and sidewall covers a portion of the first conductive pad on the first surface. An electrically conductive layer on part of the insulator layer on the first conductive pad and sidewall is in electrical contact with the second conductive pad. The insulator layer prevents the conductive layer from making electrical contact between the first and second conductive pads.

Abstract translation: 描述半导体器件，制造半导体器件的方法和电路封装组件。 半导体器件可以具有带有第一和第二表面的半导体衬底和它们之间的侧壁。 第一和第二表面上的第一和第二导电焊盘与衬底中对应的第一和第二半导体器件结构电接触。 第一表面和侧壁上的绝缘体层覆盖第一表面上的第一导电焊盘的一部分。 在第一导电焊盘和侧壁上的绝缘体层的一部分上的导电层与第二导电焊盘电接触。 绝缘体层防止导电层在第一和第二导电焊盘之间形成电接触。

公开(公告)号：US20130026615A1

公开(公告)日：2013-01-31

申请号：US13193474

申请日：2011-07-28

Applicant: Yuping Gong ,  Yan Xun Xue

Inventor： Yuping Gong ,  Yan Xun Xue

IPC: H01L21/60 ,  H01L23/495

CPC classification number: H01L23/49537 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49562 ,  H01L23/49568 ,  H01L2224/16245 ,  H01L2224/32245

Abstract: A double-side exposed semiconductor device includes an electric conductive first lead frame attached on top of a thermal conductive but electrical nonconductive second lead frame and a semiconductor chip flipped and attached on top of the first lead frame. The gate and source electrodes on top of the flipped chip form electrical connections with gate and source pins of the first lead frame respectively. The flipped chip and center portions of the first and second lead frames are then encapsulated with a molding compound, such that the heat sink formed at the center of the second lead frame and the drain electrode at bottom of the semiconductor chip are exposed on two opposite sides of the semiconductor device. Thus, heat dissipation performance of the semiconductor device is effectively improved without increasing the size of the semiconductor device.

Abstract translation: 双面露出的半导体器件包括安装在导热但不导电的第二引线框架的顶部的导电第一引线框架和翻转并附接在第一引线框架顶部上的半导体芯片。 翻转芯片顶部的栅极和源极电极分别与第一引线框架的栅极和源极引脚形成电连接。 第一和第二引线框架的翻转芯片和中心部分然后用模塑料封装，使得形成在第二引线框架的中心处的散热器和在半导体芯片的底部的漏电极暴露在两个相对的 半导体器件的侧面。 因此，在不增加半导体器件的尺寸的情况下，有效地提高了半导体器件的散热性能。

公开(公告)号：US08362606B2

公开(公告)日：2013-01-29

申请号：US12846743

申请日：2010-07-29

Applicant: Yueh-Se Ho ,  Yan Xun Xue

Inventor： Yueh-Se Ho ,  Yan Xun Xue

IPC: H01L23/12 ,  H01L21/00

CPC classification number: H01L23/485 ,  H01L21/768 ,  H01L23/3114 ,  H01L23/4824 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/41741 ,  H01L29/42372 ,  H01L29/7802 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/06182 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/03 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor device, a method of manufacturing semiconductor devices and a circuit package assembly are described. A semiconductor device can have a semiconductor substrate with first and second surfaces and a sidewall between them. First and second conductive pads on the first and second surfaces are in electrical contact with corresponding first and second semiconductor device structures in the substrate. An insulator layer on the first surface and sidewall covers a portion of the first conductive pad on the first surface. An electrically conductive layer on part of the insulator layer on the first conductive pad and sidewall is in electrical contact with the second conductive pad. The insulator layer prevents the conductive layer from making electrical contact between the first and second conductive pads.

Abstract translation: 描述半导体器件，制造半导体器件的方法和电路封装组件。 半导体器件可以具有带有第一和第二表面的半导体衬底和它们之间的侧壁。 第一和第二表面上的第一和第二导电焊盘与衬底中相应的第一和第二半导体器件结构电接触。 第一表面和侧壁上的绝缘体层覆盖第一表面上的第一导电焊盘的一部分。 在第一导电焊盘和侧壁上的绝缘体层的一部分上的导电层与第二导电焊盘电接触。 绝缘体层防止导电层在第一和第二导电焊盘之间形成电接触。

公开(公告)号：US20120248593A1

公开(公告)日：2012-10-04

申请号：US13494219

申请日：2012-06-12

Applicant: Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu

Inventor： Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu

IPC: H01L23/495

CPC classification number: H01L24/49 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01067 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/84

Abstract: A package structure for DC-DC converter disclosed herein can reduce the number of encapsulated elements as a low-side MOSFET chip can be stacked above the high-side MOSFET chip of a first die pad, through die pads of different thicknesses or interposers with joint parts of different thicknesses; moreover, it further reduces the size of the entire semiconductor package as a number of bond wires are contained in the space between the controller and the low-side MOSFET chip. Moreover, electrical connection between the top source electrode pin and the bottom source electrode pin of the low-side MOSFET chip is realized with a metal joint plate, such that when the DC-DC converter is sealed with plastic, the metal joint plate can be exposed outside to improve the thermal performance and effectively reduce the thickness of the semiconductor package.

Abstract translation: 本文公开的用于DC-DC转换器的封装结构可以减少封装元件的数量，因为低侧MOSFET芯片可以堆叠在第一裸片焊盘的高侧MOSFET芯片上方，通过具有不同厚度的芯片焊盘或具有接头的插入件 不同厚度的零件; 而且，由于控制器和低侧MOSFET芯片之间的空间中包含多个接合线，因此进一步减小了整个半导体封装的尺寸。 此外，利用金属接合板实现了顶部源极电极引脚和低端MOSFET芯片的底部源极电极引脚之间的电连接，使得当DC-DC转换器用塑料密封时，金属接合板可以 暴露在外面以改善热性能并有效地减小半导体封装的厚度。

公开(公告)号：US20120235289A1

公开(公告)日：2012-09-20

申请号：US13480391

申请日：2012-05-24

Applicant: Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

Inventor： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

IPC: H01L23/495 ,  H01L21/60

CPC classification number: H01L24/73 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/1184 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16245 ,  H01L2224/2784 ,  H01L2224/291 ,  H01L2224/3015 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40247 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83101 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/84385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/16151 ,  H01L2924/167 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/92 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/48247 ,  H01L2924/01014 ,  H01L2924/00014 ,  H01L2224/73103 ,  H01L2924/00

Abstract: A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process.

Abstract translation: 功率半导体封装具有超薄芯片，具有正面成型以降低基板电阻; 具有位于两侧引线上的凹槽的引线框单元提供精确的定位，用于将多个桥形金属夹连接到侧引线的前侧。 桥形金属夹具有桥结构和半或完全蚀刻的通孔，用于在制造过程中缓解多余的焊料。

公开(公告)号：US08250111B2

公开(公告)日：2012-08-21

申请号：US12394786

申请日：2009-02-27

Applicant: Matthew Albert Huras ,  Keriley Kay Romanufa ,  Aamer Sachedina ,  Xun Xue

Inventor： Matthew Albert Huras ,  Keriley Kay Romanufa ,  Aamer Sachedina ,  Xun Xue

IPC: G06F17/30

CPC classification number: G06F17/30306

Abstract: According to one embodiment of the present invention, a method of detecting and correcting hot pages in a database system includes monitoring transactions involving pages in a database and determining if one of the transactions had to wait for access to one of the pages; incrementing a page contention counter each time one of the transactions had to wait for access to one of the pages. The method then determines if the page contention counter exceeds a predetermined threshold and monitors transactions on one of the pages for which the page contention count was exceeded. The method then determines if a row was accessed in the page for which the page contention count was exceeded and increments a reference count for the accessed row. The accessed rows are flagged when the reference count exceeds a second predetermined threshold. The flagged rows are moved to another page in the database.

Abstract translation: 根据本发明的一个实施例，一种在数据库系统中检测和校正热页面的方法包括监视涉及数据库中的页面的事务，并且确定其中一个事务是否必须等待访问其中一个页面; 每次其中一个事务必须等待访问其中一个页面时，增加页面争用计数器。 该方法然后确定页面争用计数器是否超过预定阈值，并且监视超出页面争用次数的页面之一上的事务。 该方法然后确定在超出页面争用次数的页面中是否访问了一行，并增加访问行的引用计数。 当参考计数超过第二预定阈值时，所访问的行被标记。 标记的行被移动到数据库中的另一个页面。

公开(公告)号：US20120193695A1

公开(公告)日：2012-08-02

申请号：US13442757

申请日：2012-04-09

Applicant: Yan Xun Xue ,  Anup Bhalla ,  Jun Lu

Inventor： Yan Xun Xue ,  Anup Bhalla ,  Jun Lu

IPC: H01L27/06

CPC classification number: H01L23/49575 ,  H01L23/49562 ,  H01L23/49589 ,  H01L24/37 ,  H01L24/39 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/84

Abstract: A semiconductor package for power converter application comprises a low-side MOSFET chip and a high-side MOSFET chip stacking one over the other. The semiconductor package may further enclose a capacitor whereas the capacitor may be a discrete component or an integrated component on chip level with the low-side MOSFET. The semiconductor package may further comprise a PIC chip to provide a complete power converter on semiconductor chip assembly package level.

Abstract translation: 用于功率转换器应用的半导体封装包括低边MOSFET芯片和高边MOSFET芯片。 半导体封装可以进一步包围电容器，而电容器可以是分立元件或芯片级与低边MOSFET的集成元件。 半导体封装还可以包括PIC芯片，以在半导体芯片组件封装级别上提供完整的功率转换器。

公开(公告)号：US20120175706A1

公开(公告)日：2012-07-12

申请号：US13421864

申请日：2012-03-16

Applicant: Yuping Gong ,  Yan Xun Xue

Inventor： Yuping Gong ,  Yan Xun Xue

IPC: H01L29/78

CPC classification number: H01L23/49562 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49548 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/0346 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/3701 ,  H01L2224/371 ,  H01L2224/40245 ,  H01L2224/83191 ,  H01L2224/8485 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1816 ,  H01L2924/01028 ,  H01L2224/03 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2924/00012

Abstract: A method of making a chip-exposed semiconductor package comprising the steps of: plating a plurality of electrode on a front face of each chip on a wafer; grinding a backside of the wafer and depositing a back metal then separating each chips; mounting the chips with the plating electrodes adhering onto a front face of a plurality of paddle of a leadframe; adhering a tape on the back metal and encapsulating with a molding compound; removing the tape and sawing through the leadframe and the molding compound to form a plurality of packaged semiconductor devices.

Abstract translation: 一种制造芯片暴露半导体封装的方法，包括以下步骤：在晶片上的每个芯片的正面上电镀多个电极; 研磨晶片的背面并沉积后金属，然后分离每个芯片; 安装具有粘附在引线框架的多个桨叶的前面上的电镀电极的芯片; 将胶带粘附在背面金属上并用模塑料包封; 移除带子并穿过引线框架和模塑料形成多个封装的半导体器件。