公开(公告)号：US20170276705A1

公开(公告)日：2017-09-28

申请号：US15079364

申请日：2016-03-24

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Zhao Wang ,  Ajay Bhatia

IPC: G01R15/09 ,  G01R15/00

CPC classification number: G01R15/09 ,  G01R31/40

Abstract: An apparatus for detecting a change in a voltage level of a power supply is disclosed. An inverter coupled to a first power supply may generate a signal dependent upon a voltage level of a second power supply. A latch coupled to the first power supply may be set based on a first voltage level of the second power supply and a first value of the signal, and re-set based on a second voltage level of the second power supply and a second value of the signal different than the first value of the signal.

公开(公告)号：US09488692B2

公开(公告)日：2016-11-08

申请号：US14468394

申请日：2014-08-26

Applicant: Apple Inc.

Inventor： Asad A. Bawa ,  Benjamin A. Marrou ,  Christopher Ng ,  Michael R. Seningen ,  Mihir S. Sabnis ,  Zameeruddin Mohammed ,  Yi Zhao

IPC: G01R31/3185 ,  G01R31/3177

CPC classification number: G01R31/318552 ,  G01R31/3177 ,  G01R31/318541 ,  G01R31/318563 ,  G01R31/318575

Abstract: A method and apparatus for implementing mode based skew is disclosed. In one embodiment, an IC includes a number of different functional units each coupled to receive a respective one of a number of different clock signals. One or more of the functional circuit blocks includes at least two clock-gating circuits that are coupled to receive the clock signal provided to that functional circuit block. During a scan test, a first clock-gating circuit within a functional circuit block is configured to provide a first delay to the clock signal. A second clock-gating circuit within the functional circuit block may provide a second delay to the clock signal, the second delay being different from the first.

Abstract translation: 公开了一种用于实现基于模式的偏斜的方法和装置。 在一个实施例中，IC包括多个不同的功能单元，每个功能单元被耦合以接收多个不同时钟信号中的相应一个。 一个或多个功能电路块包括至少两个时钟门控电路，其被耦合以接收提供给该功能电路块的时钟信号。 在扫描测试期间，功能电路块内的第一时钟选通电路被配置为向时钟信号提供第一延迟。 功能电路块内的第二时钟选通电路可以向时钟信号提供第二延迟，第二延迟与第一延迟不同。

公开(公告)号：US09453879B2

公开(公告)日：2016-09-27

申请号：US14556798

申请日：2014-12-01

Applicant: Apple Inc.

Inventor： Brian S. Leibowitz ,  Mohamed H. Abu-Rahma ,  Michael R. Seningen

IPC: G01R31/02 ,  G01R31/28

CPC classification number: G01R31/2896 ,  G01R31/2874 ,  G01R31/31935

Abstract: An apparatus and method for determining performance of system is disclosed. While operating in a test mode, a plurality of test results may be received and stored in a memory. Each test result may be indicative of a performance of the system when the system is operating under a respective test condition. Also, during the test mode, a respective value of an operating parameter of a predetermined system element at each test condition. An association between each test result and a corresponding detected respective value of the operating parameter may be provided. During a normal operating mode, an operating value of the operating parameter may be determined. A performance level of the system based on a test value retrieved from memory dependent upon the operating value and the association may then be determined.

Abstract translation: 公开了一种用于确定系统性能的装置和方法。 当在测试模式下操作时，可以接收多个测试结果并将其存储在存储器中。 当系统在相应的测试条件下操作时，每个测试结果可以指示系统的性能。 此外，在测试模式期间，在每个测试条件下的预定系统元件的操作参数的相应值。 可以提供每个测试结果与操作参数的相应检测到的相应值之间的关联。 在正常操作模式期间，可以确定操作参数的操作值。 然后可以确定基于依赖于操作值和关联的从存储器检索的测试值的系统的性能级别。

公开(公告)号：US20140269025A1

公开(公告)日：2014-09-18

申请号：US14294318

申请日：2014-06-03

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Michael E. Runas

IPC: G11C29/50 ,  G11C7/06 ,  G11C11/418

CPC classification number: G11C11/418 ,  G11C7/06 ,  G11C7/1051 ,  G11C29/1201 ,  G11C29/50 ,  G11C29/50016 ,  G11C2029/1204 ,  G11C2029/5002

Abstract: Embodiments of a memory are disclosed that may reduce the likelihood of a miss-read while reading a weak data storage cell. The memory may include a number of data storage cells, a column multiplexer, a first sense amplifier and a second sense amplifier, and an output circuit. The gain level of the first sense amplifier may be higher than the gain level of the second sense amplifier. The output circuit may include a multiplexer and the multiplexer may be operable to controllably select one of the outputs of the first and second sense amplifiers and pass the value of the selected sense amplifier. The output circuit may include a node that couples the outputs of the first and second sense amplifiers and the outputs of the first and second sense amplifiers may be able to be set to a high impedance state.