公开(公告)号：US20120149181A1

公开(公告)日：2012-06-14

申请号：US13201125

申请日：2011-02-25

Applicant: Huicai Zhong ,  Qingqing Liang ,  Chao Zhao

Inventor： Huicai Zhong ,  Qingqing Liang ,  Chao Zhao

IPC: H01L21/24

CPC classification number: H01L21/3221

Abstract: There is provided a method for manufacturing a semiconductor wafer, comprising: performing heating so that metals dissolve into semiconductors of the wafer to form a semiconductor-metal compound; and performing cooling so that the formed semiconductor-metal compound retrogradely melt to form a mixture of the metals and the semiconductors. According to embodiments of the present invention, it is possible to achieve wafers of a high purity applicable to the semiconductor manufacture.

Abstract translation: 提供了一种制造半导体晶片的方法，包括：进行加热，使得金属溶解到晶片的半导体中以形成半导体 - 金属化合物; 并进行冷却，使得所形成的半导体 - 金属化合物逆向熔融以形成金属和半导体的混合物。 根据本发明的实施例，可以实现适用于半导体制造的高纯度晶片。

公开(公告)号：US20120139047A1

公开(公告)日：2012-06-07

申请号：US13380096

申请日：2011-02-27

Applicant: Jun Luo ,  Chao Zhao

Inventor： Jun Luo ,  Chao Zhao

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/47 ,  H01L29/66643 ,  H01L29/66772 ,  H01L29/7839

Abstract: Disclosed is a semiconductor device, comprising a substrate, a channel region in the substrate, source/drain regions on both sides of the channel region, a gate structure on the channel region, and gate sidewall spacers formed on the sidewalls of the gate structure, characterized in that each of the source/drain regions comprises an epitaxially grown metal silicide region, and dopant segregation regions are formed at the interfaces between the epitaxially grown metal silicide source/drain regions and the channel region. By employing the semiconductor device and the method for manufacturing the same according to embodiments of the present invention, the Schottkey Barrier Height of the MOSFETs with epitaxially grown ultrathin metal silicide source/drain may be lowered, thereby improving the driving capability.

Abstract translation: 公开了一种半导体器件，包括衬底，衬底中的沟道区域，沟道区两侧的源极/漏极区域，沟道区域上的栅极结构以及形成在栅极结构的侧壁上的栅极侧壁间隔物， 其特征在于，每个源极/漏极区域包括外延生长的金属硅化物区域，并且在外延生长的金属硅化物源极/漏极区域和沟道区域之间的界面处形成掺杂剂偏析区域。 通过采用根据本发明的实施例的半导体器件及其制造方法，可以降低具有外延生长的超薄金属硅化物源极/漏极的MOSFET的肖特基势垒高度，从而提高驱动能力。

公开(公告)号：US20050202222A1

公开(公告)日：2005-09-15

申请号：US11124303

申请日：2005-05-06

Applicant: Eduard Cartier ,  Jerry Chen ,  Chao Zhao

Inventor： Eduard Cartier ,  Jerry Chen ,  Chao Zhao

IPC: C01G27/00 ,  C01G27/02 ,  C23C16/40 ,  C23C16/44 ,  H01B3/10 ,  H01L21/02 ,  H01L21/28 ,  H01L21/316 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/51 ,  H01L29/78 ,  C04B35/48 ,  B32B9/00

CPC classification number: H01L21/02194 ,  C01G27/02 ,  C01P2002/72 ,  C23C16/40 ,  C23C16/405 ,  C23C16/4412 ,  H01B3/10 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02205 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02282 ,  H01L21/02356 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/31604 ,  H01L28/40 ,  H01L29/517 ,  H01L29/518 ,  Y10T428/24917 ,  Y10T428/265

Abstract: Dielectric material compositions comprising HfO2 and a second compound are disclosed. The compositions are characterized by at least a part of the compositions being in a cubic crystallographic phase. Further, semiconductor based devices comprising such dielectric material compound and method for forming such compounds are disclosed.

Abstract translation: 公开了包含HfO 2 N 2和第二化合物的介电材料组合物。 组合物的特征在于至少一部分组合物为立方晶相。 此外，公开了包含这种介电材料化合物的基于半导体的器件及其形成方法。

公开(公告)号：US10336896B2

公开(公告)日：2019-07-02

申请号：US14787041

申请日：2014-04-23

Applicant: Jie Zheng ,  Qiang Chen ,  Chao Zhao

Inventor： Jie Zheng ,  Qiang Chen ,  Chao Zhao

IPC: C12C11/02 ,  C08L33/26 ,  C08B37/00 ,  C08L5/12 ,  C08J3/075 ,  C08L5/00

Abstract: A method of forming a hybrid physically and chemically cross-linked double-network hydrogel with highly recoverable and mechanical properties in a single-pot synthesis is provided. The method comprises the steps of combining the hydrogel precursor reactants into a single pot. The hydrogel precursor reactants include water; a polysaccharide; a methacrylate monomer; an ultraviolet initiator; and a chemical crosslinker. Next the hydrogel precursor reactants are heated to a temperature higher than the melting point of the polysaccharide and this temperature is retained until the polysaccharide is in a sol state. Then the single-pot is cooled to a temperature lower than the gelation point of the polysaccharide and this temperature is retained to form a first network. Thereafter, photo-initiated polymerization of the methacrylate monomer occurs via the ultraviolet initiator to form the second network.

公开(公告)号：US20160083574A1

公开(公告)日：2016-03-24

申请号：US14787041

申请日：2014-04-23

Applicant: Jie Zheng ,  Qiang Chen ,  Chao Zhao

Inventor： Jie Zheng ,  Qiang Chen ,  Chao Zhao

IPC: C08L33/26 ,  C08L5/12

CPC classification number: C08L33/26 ,  C08B37/0039 ,  C08J3/075 ,  C08J2305/12 ,  C08J2333/26 ,  C08J2405/12 ,  C08J2433/26 ,  C08L5/00 ,  C08L5/12 ,  C08L33/10

Abstract: A method of forming a hybrid physically and chemically cross-linked double-network hydrogel with highly recoverable and mechanical properties in a single-pot synthesis is provided. The method comprises the steps of combining the hydrogel precursor reactants into a single pot. The hydrogel precursor reactants include water; a polysaccharide; a methacrylate monomer; an ultraviolet initiator; and a chemical crosslinker. Next the hydrogel precursor reactants are heated to a temperature higher than the melting point of the polysaccharide and this temperature is retained until the polysaccharide is in a sol state. Then the single-pot is cooled to a temperature lower than the gelation point of the polysaccharide and this temperature is retained to form a first network. Thereafter, photo-initiated polymerization of the methacrylate monomer occurs via the ultraviolet initiator to form the second network.

Abstract translation: 提供了在单锅合成中形成具有高可回收和机械性质的杂化物理和化学交联双网络水凝胶的方法。 该方法包括以下步骤：将水凝胶前体反应物合并成单个罐。 水凝胶前体反应物包括水; 多糖; 甲基丙烯酸酯单体; 紫外线引发剂; 和化学交联剂。 接下来将水凝胶前体反应物加热到高于多糖的熔点的温度，并保持该温度，直到多糖处于溶胶状态。 然后将单釜冷却至低于多糖的凝胶化点的温度，并保持该温度以形成第一网络。 此后，通过紫外线引发剂发生甲基丙烯酸酯单体的光引发聚合以形成第二网络。

公开(公告)号：US09202890B2

公开(公告)日：2015-12-01

申请号：US14119862

申请日：2012-12-12

Applicant: Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Chao Zhao

Inventor： Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Chao Zhao

IPC: H01L21/8249 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/2807 ,  H01L21/28123 ,  H01L29/4232 ,  H01L29/78

Abstract: A method for manufacturing a dummy gate in a gate-last process is provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines having a width ranging from 32 nm to 45 nm on the hard mask layer; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer α-Si. Correspondingly, a dummy gate in a gate-last process is also provided.

Abstract translation: 提供了一种在门最后工艺中制造虚拟栅极的方法。 该方法包括：提供半导体衬底; 在半导体衬底上生长栅极氧化层; 在栅极氧化物层上沉积底层非晶硅; 在底层非晶硅上沉积ONO结构的硬掩模; 在ONO结构化的硬掩模上沉积顶层非晶硅; 在顶层非晶硅上沉积硬掩模层; 在硬掩模层上形成宽度为32nm至45nm的光致抗蚀剂线; 根据光致抗蚀剂线蚀刻硬掩模层，顶层非晶硅，ONO结构的硬掩模和底层非晶硅，并除去光致抗蚀剂线，硬掩模层和顶层α- Si。 相应地，还提供了最后进程中的虚拟门。

公开(公告)号：US09070719B2

公开(公告)日：2015-06-30

申请号：US13577942

申请日：2011-11-18

Applicant: Huicai Zhong ,  Qingqing Liang ,  Jun Luo ,  Chao Zhao

Inventor： Huicai Zhong ,  Qingqing Liang ,  Jun Luo ,  Chao Zhao

IPC: H01L21/762 ,  H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L21/84

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor device structure, a method for manufacturing the same, and a method for manufacturing a semiconductor fin are disclosed. In one embodiment, the method for manufacturing the semiconductor device structure comprises: forming a fin in a first direction on a semiconductor substrate; forming a gate line in a second direction, the second direction crossing the first direction on the semiconductor substrate, and the gate line intersecting the fin with a gate dielectric layer sandwiched between the gate line and the fin; forming a dielectric spacer surrounding the gate line; and performing inter-device electrical isolation at a predetermined position, wherein isolated portions of the gate line form independent gate electrodes of respective devices.

Abstract translation: 公开了一种半导体器件结构，其制造方法和半导体鳍片的制造方法。 在一个实施例中，制造半导体器件结构的方法包括：在半导体衬底上沿第一方向形成翅片; 在第二方向上形成栅极线，在半导体衬底上与第一方向交叉的第二方向和与鳍状物交叉的栅极线与夹在栅极线和鳍之间的栅极电介质层形成栅极线; 形成围绕所述栅极线的介电隔离层; 以及在预定位置执行器件间电隔离，其中所述栅极线的隔离部分形成各个器件的独立栅电极。

公开(公告)号：US09049061B2

公开(公告)日：2015-06-02

申请号：US13640733

申请日：2012-04-11

Applicant: Qiuxia Xu ,  Chao Zhao ,  Gaobo Xu

Inventor： Qiuxia Xu ,  Chao Zhao ,  Gaobo Xu

IPC: H01L27/092 ,  H01L21/265 ,  H04L21/02

CPC classification number: H04L21/02 ,  H01L21/265 ,  H01L21/823807 ,  H01L29/7833 ,  H01L29/7843

Abstract: This invention discloses a CMOS device, which includes: a first MOSFET; a second MOSFET different from the type of the first MOSFET; a first stressed layer covering the first MOSFET and having a first stress; and a second stressed layer covering the second MOSFET, wherein the second stressed layer is doped with ions, and thus has a second stress different from the first stress. This invention's CMOS device and method for manufacturing the same make use of a partitioned ion implantation method to realize a dual stress liner, without the need of removing the tensile stressed layer on the PMOS region or the compressive stressed layer on the NMOS region by photolithography/etching, thus simplifying the process and reducing the cost, and at the same time, preventing the stress in the liner on the NMOS region or PMOS region from the damage that might be caused by the thermal process of the deposition process.

Abstract translation: 本发明公开了一种CMOS器件，其包括：第一MOSFET; 与第一MOSFET的类型不同的第二MOSFET; 覆盖所述第一MOSFET并具有第一应力的第一应力层; 以及覆盖所述第二MOSFET的第二应力层，其中所述第二应力层掺杂有离子，并且因此具有不同于所述第一应力的第二应力。 本发明的CMOS器件及其制造方法利用分离离子注入方法实现双重应力衬垫，而不需要通过光刻/光刻技术去除PMOS区域上的拉伸应力层或NMOS区域上的压应力层， 蚀刻，从而简化了工艺并降低了成本，并且同时防止了NMOS区域或PMOS区域上的衬垫中的应力不受由沉积工艺的热处理引起的损伤。

公开(公告)号：US09024435B2

公开(公告)日：2015-05-05

申请号：US13379347

申请日：2011-08-12

Applicant: Huicai Zhong ,  Qingqing Liang ,  Jiang Yan ,  Chao Zhao

Inventor： Huicai Zhong ,  Qingqing Liang ,  Jiang Yan ,  Chao Zhao

IPC: H01L23/34 ,  H01L23/522 ,  H01L23/467 ,  H01L23/473

CPC classification number: H01L23/522 ,  H01L23/467 ,  H01L23/473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device, a formation method thereof, and a package structure are provided. The semiconductor device comprises: a semiconductor substrate in which a metal-oxide-semiconductor field-effect transistor (MOSFET) is formed; a dielectric layer, provided on the semiconductor substrate and covering the MOSFET, wherein a plurality of interconnection structures are formed in the dielectric layer; and at least one heat dissipation path, embedded in the dielectric layer between the interconnection structures, for liquid or gas to circulate in the heat dissipation path, wherein openings of the heat dissipation path are exposed on the surface of the dielectric layer. The present invention can improve heat dissipation efficiency, and prevent chips from overheating.

Abstract translation: 提供半导体器件，其形成方法和封装结构。 半导体器件包括：形成金属氧化物半导体场效应晶体管（MOSFET）的半导体衬底; 介电层，设置在所述半导体衬底上并覆盖所述MOSFET，其中在所述电介质层中形成多个互连结构; 以及嵌入在互连结构之间的电介质层中的至少一个散热路径，用于使液体或气体在散热路径中循环，其中散热路径的开口暴露在介电层的表面上。 本发明可以提高散热效率，防止芯片过热。

公开(公告)号：US08987127B2

公开(公告)日：2015-03-24

申请号：US14361944

申请日：2012-03-23

Applicant: Jun Luo ,  Chao Zhao ,  Huicai Zhong ,  Junfeng Li ,  Dapeng Chen

Inventor： Jun Luo ,  Chao Zhao ,  Huicai Zhong ,  Junfeng Li ,  Dapeng Chen

IPC: H01L21/00 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L21/283

CPC classification number: H01L21/28097 ,  H01L21/283 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833

Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a silicic substrate; depositing a Nickel-based metal layer on the substrate and the gate stacked structure; performing a first annealing so that the silicon in the substrate reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase of metal to silicide is transformed into a Nickel-based metal silicide source/drain, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide source/drain and the substrate. The method for manufacturing the semiconductor device according to the present invention performs the annealing after implanting the doping ions into the Ni-rich phase of metal silicide, thereby improving the solid solubility of the doping ions and forming a segregation region of highly concentrated doping ions, thus the SBH between the Nickel-based metal silicide and the silicon channel is effectively reduced, and the driving capability of the device is improved.

Abstract translation: 本发明公开了一种制造半导体器件的方法，包括：在硅衬底上形成栅层叠结构; 在基板上沉积镍基金属层和栅极堆叠结构; 进行第一退火，使得衬底中的硅与镍基金属层反应形成金属硅化物的富Ni相; 通过将掺杂离子注入到金属硅化物的富Ni相中来进行离子注入; 进行第二退火，使得金属与硅化物的富Ni相转变为镍基金属硅化物源极/漏极，同时在镍基金属硅化物源之间的界面处形成掺杂离子的偏析区域 /漏极和衬底。 根据本发明的制造半导体器件的方法在将掺杂离子注入到金属硅化物的富Ni相中之后进行退火，从而提高掺杂离子的固溶度并形成高浓度掺杂离子的偏析区域， 因此有效地降低了镍基金属硅化物与硅通道之间的SBH，提高了器件的驱动能力。