公开(公告)号：US20200111798A1

公开(公告)日：2020-04-09

申请号：US16152454

申请日：2018-10-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bipul C. Paul ,  Ruilong Xie

IPC: H01L27/11 ,  H01L23/528 ,  H01L21/768

Abstract: Disclosed are structures with a complementary field effect transistor (CFET) and a buried metal interconnect that electrically connects a source/drain region of a lower-level transistor of the CFET with another device. The structure can include a memory cell with first and second CFETs, where each CFET includes a pull-up transistor stacked on and having a common gate with a pull-down transistor and each pull-down transistor has a common source/drain region with a pass-gate transistor. The metal interconnect connects a lower-level source/drain region of the first CFET (i.e., the common source/drain region of first pass-gate and pull-up transistors) to the common gate of the second CFET (i.e., to the common gate of second pull-down and pull-up transistors). Formation methods include forming an interconnect placeholder during lower-level source/drain region formation. After upper-level source/drain regions and replacement metal gates are formed, the interconnect placeholder is exposed, removed and replaced with a metal interconnect.

公开(公告)号：US10510392B1

公开(公告)日：2019-12-17

申请号：US16047882

申请日：2018-07-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Bipul C. Paul ,  Akhilesh Jaiswal ,  Ajey Poovannummoottil Jacob ,  William Taylor ,  Danny Pak-Chum Shum

IPC: G11C11/16

Abstract: Integrated circuits, memory arrays and methods for operating integrated circuit devices are provided. In an embodiment, an integrated circuit includes a selected column of bit cells, wherein each bit cell in the selected column is coupled to a source line and coupled to a bit line. Further, the integrated circuit includes a first column of bit cells laterally adjacent the selected column, wherein each bit cell in the first column is coupled to the source line. Also, the integrated circuit includes a second column of bit cells laterally adjacent the selected column, wherein each bit cell in the second column is coupled to the bit line.

公开(公告)号：US20190279990A1

公开(公告)日：2019-09-12

申请号：US15917027

申请日：2018-03-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bipul C. Paul ,  Joseph Versaggi ,  Steven Bentley

IPC: H01L27/11 ,  G11C11/412 ,  G11C11/419 ,  H01L51/05 ,  H01L29/78 ,  H01L29/06 ,  H01L27/28

Abstract: Structures for a bitcell of a two-port static random access memory (SRAM) and methods for forming a structure for a bitcell of a two-port SRAM. A storage element of the SRAM includes a first pull-up (PU) vertical-transport field-effect transistor (VTFET) with a fin, a first pull-down (PD) VTFET with a fin that is aligned in a first row with the fin of the first PU VTFET, a second PU VTFET with a fin, and a second PD VTFET with a fin that is aligned in a second row with the fin of the second PU VTFET. The structure further includes a read port coupled with the storage element. The read port includes a read port pull-down (RPD) VTFET with a fin and a read port access (RPG) VTFET with a fin that is aligned in a third row with the fin of the RPG VTFET.

公开(公告)号：US10304833B1

公开(公告)日：2019-05-28

申请号：US15898812

申请日：2018-02-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Puneet Harischandra Suvarna ,  Bipul C. Paul ,  Ruilong Xie ,  Bartlomiej Jan Pawlak ,  Lars W. Liebmann ,  Daniel Chanemougame ,  Nicholas V. LiCausi ,  Andreas Knorr

IPC: H01L29/775 ,  H01L29/78 ,  H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L27/12

Abstract: A device includes a first nano-sheet of a first semiconductor material. First source/drain regions are positioned adjacent ends of the first nano-sheet. A first dielectric material is positioned above the first source/drain regions. A second nano-sheet of a second semiconductor material is positioned above the first nano-sheet. Second source/drain regions are positioned adjacent ends of the second nano-sheet and above the first dielectric material. A gate structure has a first portion capacitively coupled to the first nano-sheet and a second portion capacitively coupled to the second nano-sheet. A first source/drain contact contacts a first portion of the second source/drain regions in a first region where the first and second source/drain regions do not vertically overlap. The first source/drain contact has a first depth that extends below a height of an upper surface of the first source/drain regions in a second region where the first and second source/drain regions vertically overlap.

公开(公告)号：US10121713B1

公开(公告)日：2018-11-06

申请号：US15589126

申请日：2017-05-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bipul C. Paul ,  Hajime Terazawa ,  Joseph Versaggi

IPC: H01L21/66 ,  H01L27/11 ,  G01R31/00 ,  G01R31/28

CPC classification number: H01L22/34 ,  G01R31/00 ,  G01R31/2856 ,  H01L22/14 ,  H01L27/1104

Abstract: Disclosed are an in-kerf test structure and testing method for testing an on-chip device. The structure includes at least one test component with at least one test device and adjoining dummy devices connected to the test device. Each adjoining dummy device has proximal node(s) directly connected to a test device and distal node(s) that are not directly connected to a test device. The nodes of each test device and the distal nodes of each adjoining dummy device are connected to input/output pads. During testing the input/output pads are used to bias the nodes of a selected test device as well as the distal node(s) of any adjoining dummy device. By biasing the distal node(s) of an adjoining dummy device, random accumulation of potential thereon is avoided and current contributions from the adjoining dummy device(s) to a current measurement taken from the selected test device can be accurately determined.

公开(公告)号：US10109637B1

公开(公告)日：2018-10-23

申请号：US15856205

申请日：2017-12-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Randy W. Mann ,  Bipul C. Paul

IPC: H01L27/11 ,  H01L23/528 ,  H01L23/522 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45

Abstract: The disclosure provides integrated circuit (IC) structure including: a substrate; a shallow trench isolation (STI) positioned between the first and second regions of the substrate; a first transistor with a channel region is positioned on the first region of the substrate, and spacer positioned on the first region of the substrate and the STI; and a gate metal positioned on the spacer. The gate metal includes a gate contact region positioned over the first source/drain region of the substrate, and surrounding the channel region. Across-couple region extends laterally from the gate contact region to the source/drain region of a second transistor formed on the second region of the substrate.

公开(公告)号：US09929236B1

公开(公告)日：2018-03-27

申请号：US15624762

申请日：2017-06-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bipul C. Paul ,  Kwan-Yong Lim

IPC: H01L29/786 ,  H01L29/06 ,  H01L27/11 ,  H01L29/423 ,  H01L21/8238

CPC classification number: H01L27/1108 ,  H01L21/823814 ,  H01L21/823885

Abstract: Methods form structures to include a first pair of complementary transistors (having first and second transistors) and a second pair of complementary transistors (having third and fourth transistors). An active area of the first transistor contacts an active area of the second transistor along a first common edge that is straight, and an active area of the third transistor contacts an active area of the fourth transistor along a second common edge that is straight and parallel to the first common edge. The active area of the second transistor has a third edge, opposite the first common edge, that has a non-linear shape, and the active area of the third transistor has a fourth edge, opposite the second common edge, that has the same non-linear shape. The non-linear shape of the third edge faces and is inverted relative to the non-linear shape of the fourth edge.