公开(公告)号：US10797154B2

公开(公告)日：2020-10-06

申请号：US15190778

申请日：2016-06-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Andrew M. Greene ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/283 ,  H01L27/088 ,  H01L29/417 ,  H01L23/485 ,  H01L29/78 ,  H01L23/532 ,  H01L23/535 ,  H01L21/306 ,  H01L21/8234 ,  H01L29/08

Abstract: A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer. The first dielectric layer is isotropically etched to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible. The isotropic etching is super selective to remove the first dielectric layer relative to the first material and relative to gate structures disposed between the source and drain regions. Metal is deposited in the trenches to form silicide contacts to the source and drain regions.

公开(公告)号：US10546785B2

公开(公告)日：2020-01-28

申请号：US15454445

申请日：2017-03-09

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES INC. ,  Lam Research Corporation

Inventor： Georges Jacobi ,  Vimal K. Kamineni ,  Randolph F. Knarr ,  Balasubramanian Pranatharthiharan ,  Muthumanickam Sankarapandian

IPC: H01L21/8234 ,  H01L21/768 ,  H01L21/28 ,  H01L29/40 ,  H01L29/66

Abstract: After forming a material stack including a gate dielectric, a work function metal and a cobalt gate electrode in a gate cavity formed by removing a sacrificial gate structure, the cobalt gate electrode is recessed by oxidizing the cobalt gate electrode to provide a cobalt oxide layer on a surface of the cobalt gate electrodes and removing the cobalt oxide layer from the surface of the cobalt gate electrodes by a chemical wet etch. The oxidation and oxide removal steps can be repeated until the cobalt gate electrode is recessed to any desired thickness. The work function metal can be recessed after the recessing of the cobalt gate electrode is completed or during the recessing of the cobalt gate electrode.

公开(公告)号：US10340189B2

公开(公告)日：2019-07-02

申请号：US15689565

申请日：2017-08-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Balasubramanian Pranatharthiharan ,  Junli Wang ,  Ruilong Xie

IPC: H01L29/51 ,  H01L21/8234 ,  H01L29/08 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L29/10 ,  H01L21/84 ,  H01L27/12

Abstract: A method of forming a semiconductor device that includes providing a first set of fin structures having a first pitch, and a second set of fin structure having a second pitch, wherein the second pitch is greater than the first pitch. An epitaxial semiconductor material on the first and second set of fin structures. The epitaxial semiconductor material on the first fin structures is merging epitaxial material and the epitaxial material on the second fin structures is non-merging epitaxial material. A dielectric liner is formed atop the epitaxial semiconductor material that is present on the first and second sets of fin structures. The dielectric liner is removed from a portion of the non-merging epitaxial material that is present on the second set of fin structures. A bridging epitaxial semiconductor material is formed on exposed surfaces of the non-merging epitaxial material.

公开(公告)号：US10186599B1

公开(公告)日：2019-01-22

申请号：US15655547

申请日：2017-07-20

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc. ,  SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su Chen Fan ,  Andrew M. Greene ,  Sean Lian ,  Balasubramanian Pranatharthiharan ,  Mark V. Raymond ,  Ruilong Xie

IPC: H01L21/82 ,  H01L29/66 ,  H01L21/033 ,  H01L21/768 ,  H01L21/285 ,  H01L29/49 ,  H01L29/51

Abstract: Techniques for forming self-aligned contacts by forming gate sidewall spacers and gates before forming the contacts are provided. In one aspect, a method of forming self-aligned contacts includes the steps of: forming multiple gate sidewall spacers on a substrate; burying the gate sidewall spacers in a dielectric; forming gate trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which gates will be formed; forming the gates in the gate trenches; forming contact trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which the self-aligned contacts will be formed; and forming the self-aligned contacts in the contact trenches. A device structure having self-aligned contacts is also provided.

公开(公告)号：US10170482B2

公开(公告)日：2019-01-01

申请号：US15055571

申请日：2016-02-27

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Balasubramanian Pranatharthiharan ,  Hui Zang

IPC: H01L29/78 ,  H01L27/11 ,  H01L29/06 ,  H01L27/088 ,  H01L29/66 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/76 ,  H01L21/762 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/033 ,  H01L21/308 ,  H01L21/265

Abstract: A method for preventing epitaxial growth in a semiconductor device is described. The method includes cutting the fins of FinFET structure to form a set of exposed fin ends. A set of sidewall spacers are formed on the set of exposed fin ends, forming a set of spacer covered fin ends. The set of sidewall spacers prevent epitaxial growth at the set of spacer covered fin ends. A semiconductor device includes a set of fin structures having a set of fin ends. A set of inhibitory layers are disposed at the set of fin ends to inhibit excessive epitaxial growth at the fin ends.

公开(公告)号：US10002792B2

公开(公告)日：2018-06-19

申请号：US15624156

申请日：2017-06-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Huiming Bu ,  Andrew M. Greene ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L27/088 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L21/823475 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76837 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795

Abstract: A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.

公开(公告)号：US20180006141A1

公开(公告)日：2018-01-04

申请号：US15597650

申请日：2017-05-17

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Jody Fronheiser ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Balasubramanian Pranatharthiharan ,  Mark Raymond ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/285 ,  H01L23/535 ,  H01L21/02

CPC classification number: H01L21/76895 ,  H01L21/02068 ,  H01L21/285 ,  H01L21/28525 ,  H01L21/76814 ,  H01L21/76831 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/0895 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/66795 ,  H01L29/785

Abstract: Forming a contact is disclosed. A trench through an interlayer dielectric layer is opened down to a substrate. The interlayer dielectric layer is formed on the substrate such that the substrate is the bottom surface of the trench. A cleaning process of the trench is performed. The bottom surface of the trench is recessed. A trench contact epitaxial layer is formed in the trench. An oxide layer is formed on top of the trench contact epitaxial layer in the trench. A metal oxide layer is formed on top of the oxide layer in the trench. A metal contact is formed on top of the metal oxide layer, where the oxide layer and the metal oxide layer together form a dipole layer.

公开(公告)号：US09812368B2

公开(公告)日：2017-11-07

申请号：US15289158

申请日：2016-10-08

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Balasubramanian Pranatharthiharan ,  Hui Zang

IPC: H01L21/8236 ,  H01L21/8238 ,  H01L27/11 ,  H01L29/78 ,  H01L21/304 ,  H01L29/66

CPC classification number: H01L27/1104 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/3043 ,  H01L21/324 ,  H01L21/76 ,  H01L21/76224 ,  H01L21/8221 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/1116 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: The method for preventing epitaxial growth in a semiconductor device begins with cutting a set of long fins into a set of fins of a FinFET structure. Each of the set of fins has respective cut faces located at the fin ends of a set of fin ends. A photoresist layer is patterned over the set of fin ends on the set of fins of the FinFET structure. The set of fins are isolated from one another by a first dielectric material. The photoresist is patterned over the set of fin ends so that it differs from the photoresist pattern over other areas of the FinFET structure. A set of dielectric blocks is formed on the set of fin ends using the photoresist pattern. The set of dielectric blocks prevents epitaxial growth at the set of fin ends in a subsequent epitaxial growth step.

公开(公告)号：US09806078B1

公开(公告)日：2017-10-31

申请号：US15341240

申请日：2016-11-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Christopher Prindle ,  Tenko Yamashita ,  Balasubramanian Pranatharthiharan ,  Pietro Montanini ,  Soon-Cheon Seo

IPC: H01L21/8238 ,  H01L29/78 ,  H01L27/092 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L27/0924 ,  H01L21/31055 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7856

Abstract: FinFET spacer formation includes, for example, providing an intermediate semiconductor structure having a substrate having one or more fin having a first and a second plurality of gates disposed thereon, and a first plurality of spacers disposed on sides of the first and second plurality of gates, depositing a first liner on the structure, depositing a fill material at a level along inner portions of the first liner between the gates adjacent to the one or more fin, removing outer portions of the first spacers and the first liner away from the fill material, the remaining portions of the first spacers and the first liner defining a first thickness, and depositing a second liner having a second thickness over the gates and over the remaining portions of the first spacers and the first liner, and the fill material, and wherein the first thickness is greater than the second thickness.

公开(公告)号：US20170287785A1

公开(公告)日：2017-10-05

申请号：US15624156

申请日：2017-06-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Huiming Bu ,  Andrew M. Greene ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/02 ,  H01L21/768 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L21/823475 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76837 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795

Abstract: A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.