公开(公告)号：US11538633B2

公开(公告)日：2022-12-27

申请号：US16306889

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim

IPC: H01G4/224 ,  H01G4/005 ,  H01L23/16 ,  H01L49/02 ,  H05K1/02 ,  H05K3/28

Abstract: Electronic device package stiffener and capacitor technology is disclosed. A combination stiffener and capacitor can include a structural material configured to be coupled to a substrate. The structural material can have a shape configured to provide mechanical support for the substrate. The combination stiffener and capacitor can also include first and second electrodes forming a capacitor. An electronic device package and a package substrate configured to receive the combination stiffener and capacitor are also disclosed.

公开(公告)号：US20220139814A1

公开(公告)日：2022-05-05

申请号：US17579186

申请日：2022-01-19

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Min Suet Lim ,  Jiun Hann Sir ,  Hoay Tien Teoh ,  Jimmy Huat Since Huang

IPC: H01L23/498 ,  H05K1/18 ,  H01L21/56 ,  H01L23/522 ,  H01L23/00 ,  H01L23/538

Abstract: An electronic package with passive components located between a first substrate and a second substrate. The electronic package can include a first substrate including a device interface for communication with an electronic device. An interposer can be electrically coupled to the first substrate. A second substrate can be offset from the first substrate at a distance. The second substrate can be electrically coupled to the first substrate through the interposer. A passive component can be attached to one of the first substrate or the second substrate. The passive component can be located between the first substrate and the second substrate. A height of the passive component can be is less than the distance between the first substrate and the second substrate. The second substrate can include a die interface configured for communication with a die. The die interface can be communicatively coupled to the passive component.

公开(公告)号：US20220110214A1

公开(公告)日：2022-04-07

申请号：US17550746

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Martin M. Chang ,  Tin Poay Chuah ,  Eng Huat Goh ,  Chu Aun Lim ,  Min Suet Lim

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/14 ,  H05K1/02 ,  H05K3/30

Abstract: An apparatus comprising a package comprising a first side to interface with at least one chip; and a second side to interface with a circuit board, the second side opposite to the first side, wherein the second side comprises a non-stepped portion comprising a first plurality of conductive contacts; and a stepped portion that protrudes from the non-stepped portion, the stepped portion comprising a second plurality of conductive contacts.

公开(公告)号：US11211714B2

公开(公告)日：2021-12-28

申请号：US16462516

申请日：2017-11-21

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Min Suet Lim ,  Boon Ping Koh ,  Wil Choon Song ,  Khang Choong Yong

IPC: H01Q13/18 ,  H01Q1/38 ,  H01Q1/48 ,  H01Q21/28

Abstract: Embodiments herein disclose techniques for apparatuses and methods for making a slot antenna on a PCB with a cutout. A PCB may include a metal layer. The metal layer may include a cavity to be a first radiating element of an antenna, and a slot to be a second radiating element of the antenna. In addition, the cavity may extend to be the cutout of the PCB through other layers of the PCB. The first and second radiating elements may provide a determined transmission frequency for the antenna. The metal layer may further include a portion of a transmission line of the antenna, and the transmission line is in contact with the cavity and the slot. A package may be affixed to the PCB, where a portion of the package may be within the cutout of the PCB. Other embodiments may be described and/or claimed.

公开(公告)号：US11205613B2

公开(公告)日：2021-12-21

申请号：US16912653

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Jiun Hann Sir ,  Eng Huat Goh ,  Poh Boon Khoo

IPC: H01L23/552 ,  H01L23/498 ,  H01L21/48

Abstract: A molded frame interconnect includes power, ground and signal frame interconnects in a molded mass, that encloses an integrated-circuit package precursor, which is inserted into the frame, and coupled to the frame interconnects by a build-up redistribution layer.

公开(公告)号：US11172581B2

公开(公告)日：2021-11-09

申请号：US16003970

申请日：2018-06-08

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Min Suet Lim ,  Tin Poay Chuah ,  Han Kung Chua

IPC: H05K3/00 ,  H05K3/46 ,  H05K1/02 ,  H05K1/18 ,  H05K3/30

Abstract: Disclosed herein is a multi-planar circuit board, as well as related structures and methods. In an embodiment, a circuit board may include a first surface, a first section having the first surface in a first plane, a second section having the first surface in a second plane, and a third section connecting the first and second sections, where the third section defines a gradient between the first and second planes, and where all sections are sections within a contiguous board. In another embodiment, circuit board may further include a first component having a first thickness coupled on the first face of the first section, and a second component having a second thickness, greater than the first component, coupled on the first face of the second section, where the second section is in a lower plane, and where the overall thickness is the circuit board thickness plus the second thickness.

公开(公告)号：US20210183775A1

公开(公告)日：2021-06-17

申请号：US17024263

申请日：2020-09-17

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Eng Huat Goh ,  MD Altaf Hossain

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/522 ,  H01L21/56 ,  H01L49/02

Abstract: Disclosed embodiments include die-edge level passive devices for integrated-circuit device packages that provide a low-loss path to active and passive devices, by minimizing inductive loops.

公开(公告)号：US10861839B2

公开(公告)日：2020-12-08

申请号：US16531688

申请日：2019-08-05

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Hoay Tien Teoh

IPC: H01L25/18 ,  H01L23/48 ,  H01L25/065 ,  H01L25/10 ,  H01L23/13 ,  H01L23/538 ,  H01L23/36 ,  H01L23/00 ,  H01L21/48 ,  H01L23/367 ,  H01L25/00

Abstract: Donut-shaped Dynamic Random Access Memory (DRAM) includes a hole that fits around a processor, such that the DRAM and the processor are adjacent to one another on an Integrated Circuit (IC) package. In an embodiment, a heat spreader is mounted on top of the processor and covers a top of the DRAM without touching the DRAM.

公开(公告)号：US10856454B2

公开(公告)日：2020-12-01

申请号：US16535766

申请日：2019-08-08

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Yew San Lim ,  Jia Yan Go ,  Tin Poay Chuah ,  Eng Huat Goh

IPC: H05K9/00 ,  H05K3/46 ,  H05K1/11

Abstract: Apparatus and method for providing an electromagnetic interference (EMI) shield for removable engagement with a printed circuit board (PCB). A shaped electrically conductive member has a substantially planar member portion with multiple lateral member edges. The sidewalls are disposed at respective lateral member edges and are substantially orthogonal to the substantially planar member portion. At least one of the sidewalls includes at least one first snap-fit latching feature to engage a respective complementary second snap-fit latching feature disposed at one or more of multiple peripheral portions of a PCB.

公开(公告)号：US20200328151A1

公开(公告)日：2020-10-15

申请号：US16384348

申请日：2019-04-15

Applicant: Intel Corporation

Inventor： Jiun Hann Sir ,  Poh Boon Khoo ,  Eng Huat Goh ,  Amruthavalli Pallavi Alur ,  Debendra Mallik

IPC: H01L23/522 ,  H01L23/00

Abstract: An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate.