公开(公告)号：US20170092575A1

公开(公告)日：2017-03-30

申请号：US15370432

申请日：2016-12-06

Applicant: Intel Corporation

Inventor： Mathew J. Manusharow ,  Daniel N. Sobieski ,  Mihir K. Roy ,  William J. Lambert

IPC: H01L23/498 ,  H01L23/00 ,  H05K1/16 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/02263 ,  H01L21/28556 ,  H01L21/32 ,  H01L21/3205 ,  H01L21/4857 ,  H01L21/768 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/1205 ,  H05K1/162

Abstract: A hybrid pitch package includes a standard package pitch zone of the package having only standard package pitch sized features that is adjacent to a smaller processor pitch sized zone of the package having smaller processor pitch sized features. The package may be formed by obtaining a package having standard package pitch sized features (such as from another location or a package processing facility), forming a protective mask over a standard package pitch zone of the package that is adjacent to a smaller processor pitch sized zone on the package, and then forming smaller processor pitch sized features (such as contacts, traces and interconnects) in the smaller processor pitch sized zone at a chip fabrication processing facility. The smaller processor pitch sized features can be directly connected to (thus reducing the package connection area needed) a chip or device having processor pitch sized features (e.g., exposed contacts).

公开(公告)号：US09275971B2

公开(公告)日：2016-03-01

申请号：US14495396

申请日：2014-09-24

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Zhiguo Qian ,  Mathew J. Manusharow

IPC: H01L21/28 ,  H01L21/76 ,  H01L23/00 ,  H01L23/538 ,  H01L21/02 ,  H01L21/306 ,  H01L21/768

CPC classification number: H01L23/5385 ,  H01L21/02164 ,  H01L21/30604 ,  H01L21/486 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/4821 ,  H01L23/5381 ,  H01L23/5382 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2224/0401

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及可嵌入封装组件中的桥互连组件的技术和配置。 在一个实施例中，包装组件包括被配置为在第一管芯和第二管芯之间布置电信号的封装衬底和嵌入在封装衬底中并被配置为在第一管芯和第二管芯之间布置电信号的桥， 包括桥接基板，通过桥接基板形成的一个或多个通孔通孔（THV）和布置在桥接基板的表面上的一个或多个走线，以在第一管芯和第二管芯之间布置电信号。 包括迹线和桥互连组件的接地平面的布线特征可以由气隙分开。 可以描述和/或要求保护其他实施例。