公开(公告)号：US10191724B2

公开(公告)日：2019-01-29

申请号：US15299664

申请日：2016-10-21

Applicant: Intel Corporation

Inventor： Bu Qi Cheng ,  Wei-Yu Chen ,  Guei-Yuan Lueh

IPC: G06F9/44 ,  G06F8/41 ,  G06F9/30 ,  G06F9/38 ,  G06T1/20

Abstract: Methods and apparatus relating to techniques for compiler-based instruction scoreboarding. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to remove unnecessary dependence edges from a data dependency graph, partition the data dependency graph into a plurality of sub-graphs, determine a live range for each of the plurality of sub-graphs, and assign a scoreboard entry to each of the plurality of sub-graphs, wherein sub-graphs which have interfering live ranges are assigned different scoreboard entries. Other embodiments are also disclosed and claimed.

公开(公告)号：US09886734B2

公开(公告)日：2018-02-06

申请号：US13870924

申请日：2013-04-25

Applicant: Intel Corporation

Inventor： Wei-Yu Chen ,  Guei-Yuan Lueh ,  Subramaniam Maiyuran

IPC: G06T1/00 ,  G06T1/20

CPC classification number: G06T1/20

Abstract: Various embodiments are generally directed to techniques to prefetch pixel data of one or more pixels adjacent to a pixel for which pixel data is retrieved where the prefetched pixel data may be stored in noncontiguous storage locations. A device comprising a processor component and a hint generation component executed by the processor component to embed a prefetch hint in an executable read instruction, the executable read instruction to retrieve pixel data of a specified pixel and the prefetch hint to retrieve pixel data of an adjacent pixel that is geometrically adjacent to the specified pixel. Other embodiments are described and claimed.