公开(公告)号：US4945261A

公开(公告)日：1990-07-31

申请号：US329236

申请日：1989-03-27

Applicant: Michael E. Wright

Inventor： Michael E. Wright

IPC: G06F3/00 ,  G01R19/165 ,  H01H9/54 ,  H03K5/08

CPC classification number: G01R19/16557

Abstract: A level and edge sensitive input circuit can recognize a variety of types of input signals on an input line and provide a standard digital logic output for use within the equipment. The input circuit is formed from a bias circuit, two comparators, and a memory bit. The bias circuit applies a bias voltage to the input line. A first comparator inverts the state of the memory bit when the input signals are an increment above the bias voltage. The second comparator clears the state of the memory bit when the input signals are an increment below the bias voltage. In this way, the memory bit cycles through states which provide the desired output signals for use within the equipment.

公开(公告)号：US4922129A

公开(公告)日：1990-05-01

申请号：US302502

申请日：1989-01-26

Applicant: Michael E. Wright

Inventor： Michael E. Wright

IPC: H01L21/8222 ,  H01L27/082 ,  H03F3/213 ,  H03F3/343 ,  H03K17/615

CPC classification number: H03F3/3435

Abstract: A Darlington output stage is shown in which the saturation voltage is reduced to the level of a single common emitter output transistor. The circuit includes a lateral feed-forward transistor that bridges the driver transistor. A resistor is included to ensure that the driver transistor is turned off when the output transistor saturates. An IC version of the circuit is set forth in detail.