公开(公告)号：US10770011B2

公开(公告)日：2020-09-08

申请号：US15969763

申请日：2018-05-02

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Chieh-An Lin ,  Chun-Yung Cho ,  Jhih-Siou Cheng

IPC: G09G3/36

Abstract: A buffer circuit, a display module, and a display driving method are disclosed. The buffer circuit comprises a first polarity buffer, a negative polarity buffer. The first polarity buffer receives a first supply voltage and a second supply voltage to output a first reference voltage to a first resistance string. The second supply voltage is less than the first supply voltage. The negative polarity buffer receives the second supply voltage and a third supply voltage to output a negative reference voltage to a negative resistance string. The third supply voltage is less than the second supply voltage.

公开(公告)号：US20200184870A1

公开(公告)日：2020-06-11

申请号：US16445227

申请日：2019-06-19

Applicant: Novatek Microelectronics Corp.

Inventor： Po-Hsiang Fang ,  Jhih-Siou Cheng ,  Wen-Ching Huang

IPC: G09G3/20

Abstract: A source driver is provided. The source driver includes an integrated circuit chip, a sensitive circuit and at least one bump. The sensitive circuit is disposed in the integrated circuit chip. The sensitive circuit includes at least one capacitor. The at least one bump is disposed in the integrated circuit chip, and the at least one bump is adjacent to the sensitive circuit.

公开(公告)号：US20190156754A1

公开(公告)日：2019-05-23

申请号：US16120468

申请日：2018-09-04

Applicant: Novatek Microelectronics Corp.

Inventor： Jhih-Siou Cheng ,  Tzong-Honge Shieh ,  Chieh-An Lin ,  Ju-Lin Huang

IPC: G09G3/3258 ,  G06F3/041 ,  G06F3/044

Abstract: A driver of a display panel is provided. The driver includes a plurality of sensing channels and a signal convertor. The plurality of sensing channels are configured to receive a plurality of sensing signals from the display panel via a plurality of sensing lines and output the sensing signals. The signal convertor are coupled to the sensing channels and configured to receive the sensing signals from the sensing channels. The signal convertor receives the sensing signals from the sensing channels in different sequences during different sensing periods.

公开(公告)号：US20180233102A1

公开(公告)日：2018-08-16

申请号：US15954609

申请日：2018-04-17

Applicant: Novatek Microelectronics Corp.

Inventor： Ju-Lin Huang ,  Jhih-Siou Cheng

IPC: G09G3/36

CPC classification number: G09G3/3685 ,  G02F1/136286 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2320/02 ,  G09G2320/0223

Abstract: A display panel including a plurality of pixel units, a plurality of source lines, a plurality of gate lines and a plurality of common electrode lines is provided. The pixels units are arranged in array. The array includes a plurality of columns and a plurality of rows. The source lines are respectively coupled with the pixel units disposed in a same column of the columns. The gate lines are respectively coupled with the pixel units disposed in a same row of the rows. The common electrode lines and gate lines extend parallelly with each other. At least one of the source date lines, the gate lines and the common electrode lines has the line widths varied along the extension direction thereof.

公开(公告)号：US09972271B2

公开(公告)日：2018-05-15

申请号：US15152575

申请日：2016-05-12

Applicant: Novatek Microelectronics Corp.

Inventor： Ju-Lin Huang ,  Jhih-Siou Cheng

IPC: G09G3/36

CPC classification number: G09G3/3685 ,  G02F1/13 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2320/02 ,  G09G2320/0223

Abstract: A display panel including a plurality of pixel units, a plurality of source lines, a plurality of gate lines and a plurality of common electrode lines is provided. The pixels units are arranged in array. The array includes a plurality of columns and a plurality of rows. The source lines are respectively coupled with the pixel units disposed in a same column of the columns. The gate lines are respectively coupled with the pixel units disposed in a same row of the rows. The common electrode lines and gate lines extend parallelly with each other. At least one of the source date lines, the gate lines and the common electrode lines has the line widths varied along the extension direction thereof.

公开(公告)号：US09875707B2

公开(公告)日：2018-01-23

申请号：US14708303

申请日：2015-05-11

Applicant: Novatek Microelectronics Corp.

Inventor： Jhih-Siou Cheng ,  Po-Hsiang Fang ,  Po-Yu Tseng ,  Chieh-An Lin ,  Ju-Lin Huang ,  Yi-Chuan Liu

IPC: G09G3/36

CPC classification number: G09G3/3674 ,  G09G3/3648 ,  G09G2310/0213 ,  G09G2310/067 ,  G09G2320/041 ,  G09G2330/025

Abstract: A display apparatus and a gate driving method thereof are provided. The display apparatus includes a display panel and a gate driver. The display panel has a plurality of gate lines. Output terminals of the gate driver are coupled to the gate lines in a one-to-one manner. The gate driver is configured to drive the gate lines according to a scrambled scan sequence.

公开(公告)号：US09837053B1

公开(公告)日：2017-12-05

申请号：US15176131

申请日：2016-06-07

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Jhih-Siou Cheng ,  Po-Hsiang Fang

IPC: G09G5/393

CPC classification number: G09G5/393 ,  G09G3/20 ,  G09G3/3611 ,  G09G3/3677 ,  G09G2310/04 ,  G09G2310/067 ,  G09G2320/0252 ,  G09G2320/029 ,  G09G2320/103 ,  G09G2330/021 ,  G09G2330/022 ,  G09G2360/08 ,  G09G2360/12

Abstract: A display method includes steps of: receiving, by the controller, a first frame and a second frame from an input data; up-converting, by the controller, a frame rate of the input data to produce a third frame based on the first frame and the second frame; identifying, by the controller, a static image content of the third frame according to a comparison of the first frame and the second frame; controlling, by the controller, the driver circuit not to update data of pixels within a static display area of the display panel corresponding to the static image content during the period of time that the third frame is displayed by the display panel.

公开(公告)号：US20170330527A1

公开(公告)日：2017-11-16

申请号：US15152575

申请日：2016-05-12

Applicant: Novatek Microelectronics Corp.

Inventor： Ju-Lin Huang ,  Jhih-Siou Cheng

IPC: G09G3/36

CPC classification number: G09G3/3685 ,  G02F1/13 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2320/02 ,  G09G2320/0223

Abstract: A display panel including a plurality of pixel units, a plurality of source lines, a plurality of gate lines and a plurality of common electrode lines is provided. The pixels units are arranged in array. The array includes a plurality of columns and a plurality of rows. The source lines are respectively coupled with the pixel units disposed in a same column of the columns. The gate lines are respectively coupled with the pixel units disposed in a same row of the rows. The common electrode lines and gate lines extend parallelly with each other. At least one of the source date lines, the gate lines and the common electrode lines has the line widths varied along the extension direction thereof.

公开(公告)号：US20170124979A1

公开(公告)日：2017-05-04

申请号：US14925953

申请日：2015-10-28

Applicant: Novatek Microelectronics Corp.

Inventor： Ju-Lin Huang ,  Jhih-Siou Cheng

IPC: G09G5/00 ,  G02F1/133 ,  G02F1/1362 ,  H01L27/12

CPC classification number: G09G5/003 ,  G02F1/13306 ,  G02F1/136286 ,  G09G3/3648 ,  G09G2320/0223 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1259

Abstract: A display panel, a manufacturing method thereof, and a driving method thereof are provided. The display panel includes at least one source line and a plurality of pixel circuits. The source terminal of each of the pixel circuits is coupled to the source line. The pixel circuits include a near pixel circuit and a far pixel circuit. The distance from the near pixel circuit to a source driver is less than the distance from the far pixel circuit to the source driver. The input impedance (in turn-on state) of the source terminal of the near pixel circuit is greater than the input impedance (in turn-on state) of the source terminal of the far pixel circuit, so as to compensate the source line impedance difference at different locations of the same source line.

公开(公告)号：US09569989B2

公开(公告)日：2017-02-14

申请号：US13928376

申请日：2013-06-26

Applicant: Novatek Microelectronics Corp.

Inventor： Ju-Lin Huang ,  Jhih-Siou Cheng ,  Chun-Yung Cho ,  Chieh-An Lin

IPC: G09G3/00

CPC classification number: G09G3/00 ,  G09G2300/0838 ,  G09G2300/0871 ,  G09G2310/0213 ,  G09G2310/0289 ,  G09G2330/045

Abstract: A panel driver integrated circuit (IC) and a cooling method of the panel driver IC are provided. The panel driver IC includes a data encoder, a level shifter, a Digital-to-Analog Converter (DAC), a rearrangement circuit and an output buffer. The data encoder receives and selectively changes an original data for outputting to the level shifter. An input terminal and an output terminal of the level shifter are coupled to an output terminal of the data encoder and a data input terminal of the DAC, respectively. The output terminals of the rearrangement circuit are respectively coupled to the reference voltage input terminals of the DAC for providing different reference voltages. The rearrangement circuit correspondingly rearranges the order of the reference voltages according to the operation of the data encoder. An input terminal of the output buffer is coupled to an output terminal of the DAC.

Abstract translation: 提供面板驱动器集成电路（IC）和面板驱动器IC的冷却方法。 面板驱动器IC包括数据编码器，电平转换器，数模转换器（DAC），重排电路和输出缓冲器。 数据编码器接收并选择性地改变用于输出到电平移位器的原始数据。 电平移位器的输入端子和输出端子分别耦合到数据编码器的输出端子和DAC的数据输入端子。 重排电路的输出端分别耦合到DAC的参考电压输入端，以提供不同的参考电压。 重排电路根据数据编码器的操作相应地重新排列参考电压的顺序。 输出缓冲器的输入端耦合到DAC的输出端。