公开(公告)号：US20210202437A1

公开(公告)日：2021-07-01

申请号：US16952084

申请日：2020-11-19

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498

Abstract: A package structure including a redistribution circuit structure, an insulator, a plurality of conductive connection pieces, a first chip, a second chip, an encapsulant, a third chip, and a plurality of conductive terminals is provided. The redistribution circuit structure has first and second connection surfaces opposite to each other. The insulator is embedded in and penetrates the redistribution circuit structure. The conductive connection pieces penetrate the insulator. The first and second chips are disposed on the first connection surface. The encapsulant is disposed on the redistribution circuit structure and at least laterally covers the first and second chips. The third chip is disposed on the second connection surface and electrically connected to the first and second chips through the conductive connection pieces. The conductive terminals are disposed on the second connection surface and electrically connected to the first chip or the second chip through the redistribution circuit structure.

公开(公告)号：US20210202363A1

公开(公告)日：2021-07-01

申请号：US16952044

申请日：2020-11-18

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/053 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: The disclosure provides a package structure including a redistribution circuit structure, a first circuit board, a second circuit board, a first insulator, multiple conductive terminals, and a package. The redistribution circuit structure has a first connection surface and a second connection surface opposite to each other. The first circuit board and the second circuit board are disposed on the first connection surface and are connected electrically to the redistribution circuit structure. The first insulator is disposed on the first connection surface and covers the first circuit board and the second circuit board. The conductive terminals are connected electrically to and disposed on the first circuit board or the second circuit board. The package is disposed on the second connection surface and is connected electrically to the redistribution circuit structure. A manufacturing method of a package structure is also provided.

公开(公告)号：US20200328161A1

公开(公告)日：2020-10-15

申请号：US16830235

申请日：2020-03-25

Applicant: Powertech Technology Inc.

Inventor： Nan-Chun Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien

IPC: H01L23/538 ,  H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A chip package structure including a first chip, an encapsulant, a first redistribution layer, a second redistribution layer, a second chip, and a third chip is provided. The first chip has an active surface, a back side surface opposite to the active surface, a plurality of conductive vias, and a plurality of conductive connectors disposed on the back side surface. The encapsulant covers the active surface, the back side surface, and the conductive connectors. The encapsulant has a first encapsulating surface and a second encapsulating surface opposite to the first encapsulating surface. The first redistribution layer is disposed on the first encapsulating surface. The second redistribution layer is disposed on the second encapsulating surface. The second chip is disposed on the second redistribution layer. The third chip is disposed on the second redistribution layer. A manufacturing method of a chip package structure is also provided.

公开(公告)号：US20200006290A1

公开(公告)日：2020-01-02

申请号：US16019551

申请日：2018-06-27

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00

Abstract: A package structure including first and second packages is provided. The first package includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, and a plurality of conductive wire segments. The semiconductor die has an active surface and a back surface. The insulating encapsulant encapsulates the semiconductor die. The first redistribution layer is disposed on the back surface of the semiconductor die and a bottom surface of the insulating encapsulant. The first redistribution layer has a first surface and a second surface opposite to the first surface. The second redistribution layer is disposed on the active surface of the semiconductor die. The plurality of conductive wire segments electrically connects the semiconductor die to the second redistribution layer and the first redistribution layer to the second redistribution layer. The second package is stacked on the second surface of the first redistribution layer over the first package.

公开(公告)号：US20190393200A1

公开(公告)日：2019-12-26

申请号：US16016672

申请日：2018-06-25

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L21/56

Abstract: A package structure includes a first redistribution structure, a die, a plurality of conductive sheets, a plurality of conductive balls, and a first encapsulant. The first redistribution structure has a first surface and a second surface opposite to the first surface. The die has a plurality of connection pads electrically connected to the first surface of the first redistribution structure. The conductive sheets are electrically connected to the first surface of the first redistribution structure. The conductive balls are correspondingly disposed on the conductive sheets and are electrically coupled to the first surface of the first redistribution structure through the conductive sheets. The first encapsulant encapsulates the die, the conductive sheets, and the conductive balls. The first encapsulant exposes at least a portion of each conductive ball.

公开(公告)号：US10438931B2

公开(公告)日：2019-10-08

申请号：US15871117

申请日：2018-01-15

Applicant: Powertech Technology Inc.

Inventor： Han-Wen Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien ,  Nan-Chun Lin

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L21/78

Abstract: A package structure includes a first redistribution layer, a second redistribution layer, a die, a plurality of conductive pillars and a die-stacked structure. The first redistribution layer has a first surface and a second surface opposite to the first surface. The second redistribution layer is disposed above the first surface. The die is disposed between the first redistribution layer and the second redistribution layer and has an active surface and a rear surface opposite to the active surface. The active surface is adhered to the first surface, and the die is electrically connected to the first redistribution layer. The conductive pillars are disposed and electrically connected between the first redistribution layer and the second redistribution layer. The die-stacked structure is bonded on the second redistribution layer.

公开(公告)号：US20190080971A1

公开(公告)日：2019-03-14

申请号：US15705250

申请日：2017-09-14

Applicant: Powertech Technology Inc.

Inventor： Hung-Hsin Hsu ,  Shang-Yu Chang Chien ,  Nan-Chun Lin

IPC: H01L21/66 ,  G01R31/02 ,  G01R31/28 ,  H01L23/00

CPC classification number: H01L22/32 ,  G01R31/025 ,  G01R31/2853 ,  G01R31/2884 ,  G01R31/2896 ,  H01L22/14 ,  H01L22/34 ,  H01L24/02 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381

Abstract: A testing method of a packaging process includes following steps. A substrate is provided. A circuit structure is formed on the substrate. The circuit structure includes a real unit area and a dummy side rail surrounding the real unit area, and a plurality of first circuit patterns is disposed on the real unit area. A second circuit pattern is formed on the dummy side rail, and the second circuit pattern emulates the configurations of at least a portion of the first circuit patterns for operating a simulation test. In addition, a packaging structure adapted for a testing process is also mentioned.

公开(公告)号：US20190043806A1

公开(公告)日：2019-02-07

申请号：US16157108

申请日：2018-10-11

Applicant: Powertech Technology Inc.

Inventor： Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L25/04 ,  H01L25/00

Abstract: A method of manufacturing a chip package structure comprising: disposing a first semiconductor component on a first carrier, wherein the first semiconductor component comprising a first active surface and a plurality of first pads disposed on the first active surface; forming a plurality of first conductive pillars on the first pads, wherein each of the first conductive pillars is a solid cylinder comprising a top surface and a bottom surface, and a diameter of the top surface is substantially the same as a diameter of the bottom surface; forming a first encapsulant to encapsulate the first semiconductor component and the first conductive pillars, wherein the first encapsulant exposes the top surface of each of the first conductive pillars; forming a first redistribution layer on the first encapsulant, wherein the first redistribution layer is electrically connected to the first conductive pillars; and removing the first carrier.

公开(公告)号：US20180076179A1

公开(公告)日：2018-03-15

申请号：US15640595

申请日：2017-07-03

Applicant: Powertech Technology Inc.

Inventor： Hung-Hsin Hsu ,  Nan-Chun Lin ,  Shang-Yu Chang Chien

IPC: H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/5226 ,  H01L24/14 ,  H01L24/17 ,  H01L24/32 ,  H01L25/03 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0132 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2224/214 ,  H01L2924/00

Abstract: A stacked-type chip package structure includes a first chip, first terminals, a first redistribution layer, a first encapsulant, a second chip, second terminals, a second redistribution layer and through pillars. Each first chip includes a first active surface and first pads located on the first active surface. The first terminals are disposed on the first pads. The first redistribution layer is electrically connected to the first chip. The first encapsulant encapsulates the first chip and exposes top surfaces of the first terminals. The second chip is disposed over the first encapsulant. The second chip includes a second active surface and second pads located on the second active surface. The second terminals are disposed on the second pads. The second redistribution layer is electrically connected to the second chip. The through pillars electrically connect the first redistribution layer and the second redistribution layer.

公开(公告)号：US20180076158A1

公开(公告)日：2018-03-15

申请号：US15600804

申请日：2017-05-22

Applicant: Powertech Technology Inc.

Inventor： Li-Chih Fang ,  Hung-Hsin Hsu ,  Nan-Chun Lin ,  Shang-Yu Chang Chien

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768

CPC classification number: H01L24/09 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/14 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/3511 ,  H01L2924/35121 ,  H01L2924/37001

Abstract: A chip package structure includes a chip, an encapsulant, a dielectric layer and a patterned circuit layer. The chip includes an active surface and a plurality of pads disposed on the active surface. The encapsulant encapsulates the chip and exposes active surface, wherein the encapsulant includes a concave surface and a back surface opposite to the concave surface, the concave surface exposes the active surface and is dented toward the back surface. The dielectric layer covers the concave surface and the active surface and includes a plurality of openings exposing the pads, wherein the opening includes a slanted side surface and the angle between the slanted side surface and the active surface is an acute angle. The patterned circuit layer is disposed on the dielectric layer and electrically connected to the pads through the openings.