公开(公告)号：US20230186086A1

公开(公告)日：2023-06-15

申请号：US18063936

申请日：2022-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehwan MOON ,  Jinseong HEO ,  Seunggeol NAM ,  Hagyoul BAE ,  Hyunjae LEE

IPC: G06N3/08 ,  G06N3/04

CPC classification number: G06N3/08 ,  G06N3/04

Abstract: Provided is a neural network device including a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction intersecting the first direction, and a plurality of memory cells arranged at points where the plurality of word lines and the plurality of bit lines intersect one another. Each of the plurality of memory cells includes at least two ferroelectric memories connected in parallel along a word line corresponding to each of the plurality of memory cells.

公开(公告)号：US20230155026A1

公开(公告)日：2023-05-18

申请号：US17986237

申请日：2022-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hagyoul BAE ,  Dukhyun CHOE ,  Jinseong HEO ,  Yunseong LEE ,  Seunggeol NAM ,  Hyunjae LEE

IPC: H01L29/78 ,  H01L27/108 ,  H01L27/24 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L27/10805 ,  H01L27/2436 ,  H01L29/516 ,  H01L29/7833 ,  H01L29/6684

Abstract: Provided are a semiconductor device and a semiconductor apparatus including the semiconductor device. The semiconductor device includes a substrate having a channel layer comprising a dopant, a ferroelectric layer on the channel layer; and a gate on the ferroelectric layer. The channel layer has a doping concentration of 1×1015 cm−3 to 1×1021 cm−3.

公开(公告)号：US20230068904A1

公开(公告)日：2023-03-02

申请号：US17876979

申请日：2022-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Yunseong LEE ,  Hyangsook LEE ,  Sanghyun JO ,  Seunggeol NAM ,  Taehwan MOON ,  Hagyoul BAE ,  Eunha LEE ,  Junho LEE

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/10

Abstract: An electronic device includes: a substrate including a source, a drain, and a channel between the source and the drain; a gate electrode arranged above the substrate and facing the channel, the gate electrode being apart from the channel in a first direction; and a ferroelectric thin film structure between the channel and the gate electrode, the ferroelectric thin film structure including a first ferroelectric layer, a crystallization barrier layer including a dielectric material, and a second ferroelectric layer, which are sequentially arranged from the channel in the first direction. The average of sizes of crystal grains of the first ferroelectric layer may be less than or equal to the average of sizes of crystal grains of the second ferroelectric layer, and owing to small crystal grains, dispersion of performance may be improved.

公开(公告)号：US20230068706A1

公开(公告)日：2023-03-02

申请号：US17896481

申请日：2022-08-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hagyoul BAE ,  Jinseong HEO ,  Seunggeol NAM ,  Taehwan MOON ,  Yunseong LEE

IPC: H01L27/24 ,  H01L27/11582 ,  H01L27/11597

Abstract: A non-volatile memory device is provided. The nonvolatile memory device includes a metal pillar, a channel layer separated from the metal pillar and surrounding a side surface of the metal pillar, a source arranged on one end of the channel layer, a drain arranged on the other end of the channel layer, a gate insulating layer surrounding a side surface of the channel layer, and a plurality of insulating elements and a plurality of gate electrodes alternately arranged along a surface of the gate insulating layer and surrounding a side surface of the gate insulating layer.

公开(公告)号：US20220140104A1

公开(公告)日：2022-05-05

申请号：US17515969

申请日：2021-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Yunseong LEE ,  Seunggeol NAM ,  Hagyoul BAE ,  Taehwan MOON ,  Sanghyun JO

IPC: H01L29/51 ,  H01L29/78

Abstract: Provided is a ferroelectric semiconductor device including a ferroelectric layer and two or more electrode layers. The semiconductor device may include a first electrode layer and a second electrode layer which have thermal expansion coefficients less than the thermal expansion coefficient of the ferroelectric layer. The difference between the thermal expansion coefficients of the second electrode layer and the ferroelectric layer may be greater than the difference between the thermal expansion coefficients of the first electrode layer and the ferroelectric. The second electrode layer may have a thickness greater than the thickness of the first electrode layer.

公开(公告)号：US20200266153A1

公开(公告)日：2020-08-20

申请号：US16866033

申请日：2020-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae SONG ,  Seunggeol NAM ,  Yeonchoo CHO ,  Seongjun PARK ,  Hyeonjin SHIN ,  Jaeho LEE

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween. The diffusion barrier layer includes a nanocrystalline graphene (nc-G) layer. In the layer structure, the diffusion barrier layer may further include a non-graphene metal compound layer or a graphene layer together with the nc-G layer. One of the first and second material layers is an insulating layer, a metal layer, or a semiconductor layer, and the remaining layer may be a metal layer.

公开(公告)号：US20190157212A1

公开(公告)日：2019-05-23

申请号：US16257189

申请日：2019-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae SONG ,  Seunggeol NAM ,  Yeonchoo CHO ,  Seongjun PARK ,  Hyeonjin SHIN ,  Jaeho LEE

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53209 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76852 ,  H01L23/5226

Abstract: Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween. The diffusion barrier layer includes a nanocrystalline graphene (nc-G) layer. In the layer structure, the diffusion barrier layer may further include a non-graphene metal compound layer or a graphene layer together with the nc-G layer. One of the first and second material layers is an insulating layer, a metal layer, or a semiconductor layer, and the remaining layer may be a metal layer.

公开(公告)号：US20180040737A1

公开(公告)日：2018-02-08

申请号：US15423035

申请日：2017-02-02

Applicant: Samsung Electronics Co., Ltd. ,  Research & Business Foundation Sungkyunkwan University

Inventor： Seunggeol NAM ,  Wonjong YOO ,  Zheng YANG

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/24

CPC classification number: H01L29/78618 ,  H01L29/24 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/778 ,  H01L29/78681 ,  H01L29/78696 ,  H01L29/861

Abstract: Provided are electronic devices having a two-dimensional (2D) material layer. The electronic device includes an electrode layer that directly contacts an edge of the 2D material layer. The electrode layer may include a conductive material having a high work function or may have a structure in which an electrode layer includes a conductive material having a high work function and an electrode layer includes a conductive material having a low work function.

公开(公告)号：US20250066950A1

公开(公告)日：2025-02-27

申请号：US18942936

申请日：2024-11-11

Applicant: Samsung Electronics Co., Ltd. ,  UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Changseok LEE ,  Hyeonsuk SHIN ,  Hyeonjin SHIN ,  Seokmo HONG ,  Minhyun LEE ,  Seunggeol NAM ,  Kyungyeol MA

IPC: C30B29/38 ,  H01L21/02

Abstract: A boron nitride layer and a method of fabricating the same are provided. The boron nitride layer includes a boron nitride compound and has a dielectric constant of about 2.5 or less at an operating frequency of 100 kHz.

公开(公告)号：US20250015184A1

公开(公告)日：2025-01-09

申请号：US18895686

申请日：2024-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hagyoul BAE ,  Seunggeol NAM ,  Jinseong HEO ,  Sanghyun JO ,  Dukhyun CHOE

IPC: H01L29/78 ,  H01L21/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786

Abstract: Provided are a ferroelectric semiconductor device and a method of extracting a defect density of the same. A ferroelectric electronic device includes a first layer, an insulating layer including a ferroelectric layer and a first interface that is adjacent to the first layer, and an upper electrode over the insulating layer, wherein the insulating layer has a bulk defect density of 1016 cm−3 eV−1 or more and an interface defect density of 1010 cm−2 eV−1 or more.