公开(公告)号：US06750692B2

公开(公告)日：2004-06-15

申请号：US10413961

申请日：2003-04-15

Applicant: Seong-Jin Jang

Inventor： Seong-Jin Jang

IPC: G06F104

CPC classification number: G06F1/04 ,  H03K3/03

Abstract: The present invention discloses a circuit and a method for generating an internal clock signal, where the internal clock signal generation circuit includes a first delay portion for delaying an external clock signal by a first delay time, divides for dividing an output signal from the first delay portion, a first signal generator for generating a first signal with a pulse width equivalent to a skew monitor time by delaying an output signal from the divider by a second delay time and by combining the output signal from the divider with a signal delayed by the second delay time, a second signal generater for generating a second signal with a pulse width equivalent to a third delay time at a falling or rising edge of the output signal from the first delay portion, a time/digital signal converter for converting the skew monitor time equavalent to the pulse width of the first signal into first and second digital signals in response to the first signal, and a digital signal/time converter for reproducing the skew monitor time by inputting the first and the second digital signals in response to the second signal and generating the internal clock signal being delayed by a fourth delay time from the skew monitor time reproduced.

Abstract translation: 本发明公开了一种用于产生内部时钟信号的电路和方法，其中内部时钟信号产生电路包括用于将外部时钟信号延迟第一延迟时间的第一延迟部分，用于将来自第一延迟的输出信号分频 第一信号发生器，用于通过将来自分频器的输出信号延迟第二延迟时间并通过将来自分频器的输出信号与延迟第二延迟时间的信号组合，产生具有等于歪斜监视时间的脉冲宽度的第一信号 延迟时间，第二信号发生器，用于在来自第一延迟部分的输出信号的下降沿或上升沿产生具有等于第三延迟时间的脉冲宽度的第二信号;时间/数字信号转换器，用于将偏斜监视时间 响应于第一信号而将第一信号的脉冲宽度偏置为第一和第二数字信号，以及数字信号/时间转换器fo r通过响应于第二信号输入第一和第二数字信号并产生从再现的偏斜监视时间延迟第四延迟时间的内部时钟信号来再现偏斜监视时间。

公开(公告)号：US06653889B2

公开(公告)日：2003-11-25

申请号：US10188927

申请日：2002-07-02

Applicant: Seong-Jin Jang ,  Young-Hyun Jun

Inventor： Seong-Jin Jang ,  Young-Hyun Jun

IPC: G05F110

CPC classification number: G11C5/145 ,  H02M3/073

Abstract: Integrated circuit voltage generating circuits include an integrated circuit substrate, a first voltage generating circuit in the integrated substrate that is configured to generate a first voltage from a power supply voltage, and a second voltage generating circuit in the integrated circuit substrate that is configured to generate a second voltage that is different from the first voltage from the power supply voltage. A shared capacitor in the integrated circuit substrate is connected to both the first voltage generating circuit and to the second voltage generating circuit. The shared capacitor is used by the first voltage generating circuit and the second voltage generating circuit, to generate the first and second voltages.

Abstract translation: 集成电路电压产生电路包括集成电路基板，被配置为从电源电压产生第一电压的集成基板中的第一电压产生电路，以及集成电路基板中的第二电压产生电路，其被配置为产生 与电源电压的第一电压不同的第二电压。 集成电路基板中的共用电容器连接到第一电压产生电路和第二电压产生电路。 共享电容器由第一电压产生电路和第二电压产生电路用于产生第一和第二电压。

公开(公告)号：US6043697A

公开(公告)日：2000-03-28

申请号：US39337

申请日：1998-03-16

Applicant: Seong-Jin Jang

Inventor： Seong-Jin Jang

IPC: H03K19/00 ,  G06F1/04 ,  G06F1/10 ,  G06F1/12 ,  G11C11/407 ,  G11C11/409 ,  H03K5/135 ,  G11C7/00

CPC classification number: G06F1/04

Abstract: A clock signal control apparatus for a data output buffer that controls a data access time and an output signal maintaining time of the data output buffer based on a period of an input first clock signal. The apparatus includes a clock signal generator for generating a second clock signal having a period controlled by a period of a first clock signal, a clock signal controller and a data output buffer. The clock signal controller delays the second clock signal from the clock signal generator for a predetermined time, generates an output enable signal and a third clock signal in accordance with the second clock signal. A data output buffer receives a data signal, buffers the data signal in accordance with the third clock signal and the output enable signal from the clock signal controller, and generates an output data signal. The second clock signal has one of a plurality of periods based on the first clock signal.

Abstract translation: 一种用于数据输出缓冲器的时钟信号控制装置，其基于输入的第一时钟信号的周期来控制数据存取时间和保持数据输出缓冲器的时间的输出信号。 该装置包括时钟信号发生器，用于产生具有由第一时钟信号的周期控制的周期的第二时钟信号，时钟信号控制器和数据输出缓冲器。 时钟信号控制器将来自时钟信号发生器的第二时钟信号延迟预定时间，根据第二时钟信号产生输出使能信号和第三时钟信号。 数据输出缓冲器接收数据信号，根据来自时钟信号控制器的第三时钟信号和输出使能信号缓冲数据信号，并产生输出数据信号。 第二时钟信号基于第一时钟信号具有多个周期中的一个。

公开(公告)号：US5986938A

公开(公告)日：1999-11-16

申请号：US168983

申请日：1998-10-09

Applicant: Seong-Jin Jang

Inventor： Seong-Jin Jang

IPC: G11C8/10 ,  G11C8/14 ,  G11C16/06

CPC classification number: G11C8/14 ,  G11C8/10

Abstract: A wordline driver for a memory device includes a row decoder decoding externally inputted row address signals and outputting a main decoding signal and a main decoding bar signal, a wordline drive decoder decoding two lowest bits among the row address signals and outputting a global decoding signal, a local wordline driver receiving first and second signals and outputting a local wordline driving signal in accordance with the global decoding signal corresponding to the wordline drive decoder, and a sub-wordline driver coupled to the wordline drive decoder and the local wordline driver and outputting a sub-wordline driving signal to a sub-wordline in accordance with the local wordline decoding signal from the local wordline driver, and the main decoding signal and the main decoding bar signal outputted from the row decoder.

Abstract translation: 用于存储器件的字线驱动器包括行解码器解码外部输入的行地址信号并输出​​主解码信号和主解码条信号，字线驱动解码器解码行地址信号中的两个最低位并输出全局解码信号， 本地字线驱动器接收第一和第二信号并根据对应于字线驱动解码器的全局解码信号输出本地字线驱动信号，以及耦合到字线驱动解码器和本地字线驱动器的子字线驱动器， 根据来自本地字线驱动器的本地字线解码信号和从行解码器输出的主解码信号和主解码条信号将子字线驱动信号发送到子字线。

公开(公告)号：US08335291B2

公开(公告)日：2012-12-18

申请号：US12929627

申请日：2011-02-04

Applicant: Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

Inventor： Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

IPC: H04L7/00

CPC classification number: G11C7/22 ,  H03K19/0966 ,  H04L7/0008 ,  H04L7/033 ,  H04L7/10

Abstract: A semiconductor device, a parallel interface system and methods thereof are provided. The example semiconductor device may include a reference clock transmitting block generating a reference clock signal, a plurality of first transceiver blocks, each of the plurality of first transceiver blocks transmitting at least one parallel data bit signal based on one of a plurality of phase-controlled transmitting sampling clock signals and a per-pin deskew block controlling a phase of a transmitting sampling clock signal to generate the phase-controlled sampling clock signals for the respective plurality of transceiver blocks, the per-pin deskew block controlling the phase of each phase-controlled transmitting sampling clock signal based on a phase skew between a given training data bit signal, among a plurality of training data bit signals, corresponding to a given first transceiver block and the reference clock signal in a first operation mode, and based on phase skew information relating to a phase skew between a given parallel data bit signal of the at least one parallel data bit signal and the reference clock signal in a second operation mode. An example method may include reducing skew based on a comparison between a plurality of transmitted training data bit signals and a corresponding plurality of received training data bit signals in a first mode of operation and reducing skew based on received phase skew information relating to a phase skew difference between a reference signal and a parallel data bit signal in a second mode of operation.

Abstract translation: 提供半导体器件，并行接口系统及其方法。 示例性半导体器件可以包括产生参考时钟信号的参考时钟发送块，多个第一收发器块，多个第一收发器块中的每一个基于多个相位控制的多个第一收发器块中的一个发送至少一个并行数据位信号 传输采样时钟信号和控制发射采样时钟信号的相位的每引脚偏移校正块，以产生相应的多个收发器模块的相位控制的采样时钟信号，每个引脚的去偏移块控制每个相位 - 基于相对于给定的第一收发器块的多个训练数据位信号中的给定训练数据位信号与第一操作模式中的参考时钟信号之间的相位偏移以及基于相位偏移的受控发送采样时钟信号 与至少一个并行数据的给定并行数据位信号之间的相位偏移有关的信息 在第二操作模式中的位信号和参考时钟信号。 示例性方法可以包括基于在第一操作模式中的多个发送的训练数据比特信号与对应的多个接收的训练数据比特信号之间的比较来减少偏斜，并且基于接收到的相位偏移相关的相位偏移信息减少偏斜 在第二操作模式中参考信号和并行数据位信号之间的差异。

公开(公告)号：US08284624B2

公开(公告)日：2012-10-09

申请号：US12691910

申请日：2010-01-22

Applicant: Ki-Heung Kim ,  Yong-Ho Cho ,  Ji-Hoon Lim ,  Seong-Jin Jang ,  Tae-Yoon Lee

Inventor： Ki-Heung Kim ,  Yong-Ho Cho ,  Ji-Hoon Lim ,  Seong-Jin Jang ,  Tae-Yoon Lee

IPC: G11C7/04

CPC classification number: G11C7/04 ,  G01R19/16552 ,  G11C5/147 ,  H03K5/2481

Abstract: A level detector, an internal voltage generator including the level detector, and a semiconductor memory device including the internal voltage generator are provided. The internal voltage generator includes a level detector that compares a threshold voltage that varies with temperature with an internal voltage to output a comparative voltage, and an internal voltage driver that adjusts an external supply voltage in response to the comparative voltage and that outputs an internal voltage.

Abstract translation: 提供了一种电平检测器，包括电平检测器的内部电压发生器和包括内部电压发生器的半导体存储器件。 内部电压发生器包括电平检测器，其将与温度变化的阈值电压与内部电压进行比较以输出比较电压;以及内部电压驱动器，其响应于比较电压调节外部电源电压并且输出内部电压 。

公开(公告)号：US20120051164A1

公开(公告)日：2012-03-01

申请号：US13219998

申请日：2011-08-29

Applicant: Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Ju-Seop Park

Inventor： Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Ju-Seop Park

IPC: G11C29/04 ,  H01L21/336 ,  G11C7/00 ,  H01L27/088

CPC classification number: G11C11/405 ,  G11C17/16 ,  G11C17/165 ,  H01L27/101 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/7835

Abstract: A memory cell includes a selection transistor on a substrate and an antifuse on the substrate. The selection transistor includes a first gate connected to a read word line, a first gate insulation layer that insulates the first gate from the substrate, a first source region connected to a bit line, and a first drain region, an impurity concentration of the first drain region being lower than an impurity concentration of the first source region. The antifuse includes a first electrode connected to a program word line and a second electrode connected to the selection transistor.

Abstract translation: 存储单元包括衬底上的选择晶体管和衬底上的反熔丝。 选择晶体管包括连接到读字线的第一栅极，将第一栅极与衬底绝缘的第一栅极绝缘层，连接到位线的第一源极区域和第一漏极区域，第一漏极区域的杂质浓度 漏极区域低于第一源极区域的杂质浓度。 反熔丝包括连接到编程字线的第一电极和连接到选择晶体管的第二电极。

公开(公告)号：US20110249513A1

公开(公告)日：2011-10-13

申请号：US13158616

申请日：2011-06-13

Applicant: Seung-Jun Bae ,  Seong-Jin Jang

Inventor： Seung-Jun Bae ,  Seong-Jin Jang

IPC: G11C7/10

CPC classification number: H03M5/145

Abstract: DC balance encoded data is transmitted by transmitting a preamble of dummy data that is configured to provide an intermediate number of bits of a given logic value that is at least one bit of the given logic value but less than a maximum number of bits of the given logic value in the DC balance encoded data, to thereby reduce the simultaneous switching noise that is caused by transmission of a first word of DC balance encoded data. The preamble may contain one or more words of fixed and/or variable dummy data.

Abstract translation: 通过发送伪数据的前导码来发送DC平衡编码数据，该伪数据的前导码被配置为提供给定逻辑值的中间位数，该给定逻辑值是给定逻辑值的至少一位，但小于给定逻辑值的最大位数 DC平衡编码数据中的逻辑值，从而减少由DC平衡编码数据的第一字的传输引起的同时开关噪声。 前导码可以包含固定和/或可变虚拟数据的一个或多个单词。

公开(公告)号：US07961121B2

公开(公告)日：2011-06-14

申请号：US12824156

申请日：2010-06-26

Applicant: Seung-Jun Bae ,  Seong-Jin Jang

Inventor： Seung-Jun Bae ,  Seong-Jin Jang

IPC: H03M5/00

CPC classification number: H03M5/145

Abstract: DC balance encoded data is transmitted by transmitting a preamble of dummy data that is configured to provide an intermediate number of bits of a given logic value that is at least one bit of the given logic value but less than a maximum number of bits of the given logic value in the DC balance encoded data, to thereby reduce the simultaneous switching noise that is caused by transmission of a first word of DC balance encoded data. The preamble may contain one or more words of fixed and/or variable dummy data.

Abstract translation: 通过发送伪数据的前导码来发送DC平衡编码数据，该伪数据的前导码被配置为提供给定逻辑值的中间位数，该给定逻辑值是给定逻辑值的至少一位，但小于给定逻辑值的最大位数 DC平衡编码数据中的逻辑值，从而减少由DC平衡编码数据的第一字的传输引起的同时开关噪声。 前导码可以包含固定和/或可变虚拟数据的一个或多个单词。

公开(公告)号：US20110128170A1

公开(公告)日：2011-06-02

申请号：US12923858

申请日：2010-10-12

Applicant: Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

Inventor： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

IPC: H03M7/00

CPC classification number: H03K19/00346 ,  H04L25/03866 ,  H04L25/14 ,  H04L25/4908

Abstract: Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

Abstract translation: 提供半导体器件，包括所述半导体器件的系统及其方法。 半导体器件的示例可以接收被调度用于发送的数据，对接收到的数据内的比特顺序进行加扰，根据给定的伪随机序列排列的加扰顺序。 所接收的数据可以是平衡的，使得等于第一逻辑电平的接收数据内的第一比特数与等于第二逻辑电平的接收数据中的第二比特数之间的差异低于阈值。 然后可以发送平衡和加扰的接收数据。 示例半导体器件可以以任何顺序执行加扰和平衡操作。 类似地，在接收端，另一个半导体器件可以通过对发送的数据进行解扰和不平衡来解码原始数据。 可以基于发送的数据被加扰和平衡的顺序以顺序执行解扰和不平衡操作。