公开(公告)号：US10418320B2

公开(公告)日：2019-09-17

申请号：US16127275

申请日：2018-09-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey A. West ,  Byron Lovell Williams ,  David Leonard Larkin ,  Weidong Tian

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L49/02 ,  H01L21/768 ,  H01L21/02

Abstract: A method and structure suitable for, e.g., improving high voltage breakdown reliability of a microelectronic device such as a capacitor usable for galvanic isolation of two circuits. A metal plate having a top surface and a side surface is located over a first dielectric layer. A second dielectric layer of a second different material is located over the first metal plate. A dielectric structure of the first material is located over the side surface of the metal plate and over the surface of the first dielectric layer.

公开(公告)号：US10251280B2

公开(公告)日：2019-04-02

申请号：US14576708

申请日：2014-12-19

Applicant: Texas Instruments Incorporated

Inventor： Byron Lovell Williams ,  Asad Mahmood Haider ,  Licheng M. Han

IPC: H01F5/00 ,  H05K3/06 ,  H01F17/00 ,  H01F41/04

Abstract: An integrated circuit with a micro inductor or with a micro transformer with a magnetic core. A process of forming an integrated circuit with a micro inductor with a magnetic core. A process of forming an integrated circuit with a micro transformer with a magnetic core.

公开(公告)号：US10186576B2

公开(公告)日：2019-01-22

申请号：US15714682

申请日：2017-09-25

Applicant: Texas Instruments Incorporated

Inventor： Raja Selvaraj ,  Anant Shankar Kamath ,  Byron Lovell Williams ,  Thomas D. Bonifield ,  John Kenneth Arch

IPC: H01L29/06 ,  H01L21/76 ,  H01L23/522 ,  H01L27/06 ,  H01L49/02 ,  H01L21/761 ,  H01L21/265 ,  H01L23/528 ,  H01L23/00

Abstract: Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include methods of forming an integrated circuit including an isolator structure. The isolator structure includes parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator

公开(公告)号：US09806148B2

公开(公告)日：2017-10-31

申请号：US14680211

申请日：2015-04-07

Applicant: Texas Instruments Incorporated

Inventor： Raja Selvaraj ,  Anant Shankar Kamath ,  Byron Lovell Williams ,  Thomas D. Bonifield ,  John Kenneth Arch

IPC: H01L29/06 ,  H01L27/06 ,  H01L21/761 ,  H01L49/02 ,  H01L21/265 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L29/0646 ,  H01L21/265 ,  H01L21/761 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5286 ,  H01L24/05 ,  H01L27/0676 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L28/60 ,  H01L2224/48463

Abstract: Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.

公开(公告)号：US20170309702A1

公开(公告)日：2017-10-26

申请号：US15646465

申请日：2017-07-11

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Thomas D. Bonifield ,  Byron Lovell Williams

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L23/552 ,  H01L23/642 ,  H01L28/40 ,  H01L2224/48463 ,  H01L2224/49107

Abstract: High voltage integrated circuit capacitors are disclosed. In an example arrangement, A capacitor structure includes a semiconductor substrate; a bottom plate having a conductive layer overlying the semiconductor substrate; a capacitor dielectric layer deposited overlying at least a portion of the bottom plate and having a first thickness greater than about 6 um in a first region; a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region having an upper surface with a slope of greater than 5 degrees from a horizontal plane and extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and a top plate conductor formed overlying at least a portion of the capacitor dielectric layer in the first region. Methods and additional apparatus arrangements are disclosed.

公开(公告)号：US20170062552A1

公开(公告)日：2017-03-02

申请号：US15348698

申请日：2016-11-10

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Thomas D. Bonifield ,  Byron Lovell Williams

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L23/552 ,  H01L23/642 ,  H01L28/40

Abstract: High voltage integrated circuit capacitors are disclosed. In an example arrangement. A capacitor structure includes a semiconductor substrate; a bottom plate having a conductive layer overlying the semiconductor substrate; a capacitor dielectric layer deposited overlying at least a portion of the bottom plate and having a first thickness greater than about 6 um in a first region; a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region having an upper surface with a slope of greater than 5 degrees from a horizontal plane and extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and a top plate conductor formed overlying at least a portion of the capacitor dielectric layer in the first region. Methods and additional apparatus arrangements are disclosed.

Abstract translation: 公开了高压集成电路电容器。 在一个例子中。 电容器结构包括半导体衬底; 底板，其具有覆盖在半导体衬底上的导电层; 沉积在所述底板的至少一部分上并且在第一区域中具有大于约6um的第一厚度的电容器电介质层; 在第一区域的边缘处的电容器电介质中的倾斜过渡区域，所述倾斜过渡区域具有从水平面倾斜大于5度的上表面，并且从第一区域延伸到电容器电介质的第二区域 层，其具有比第一厚度低的第二厚度; 以及形成在所述第一区域中覆盖所述电容器电介质层的至少一部分的顶板导体。 公开了方法和附加装置布置。

公开(公告)号：US20160163452A1

公开(公告)日：2016-06-09

申请号：US15042319

申请日：2016-02-12

Applicant: Texas Instruments Incorporated

Inventor： Honglin Guo ,  Byron Lovell Williams

IPC: H01G2/08 ,  H01G4/018

CPC classification number: H01G2/08 ,  H01B3/306 ,  H01G4/018 ,  H01G4/18 ,  H01G4/33 ,  H01G4/40 ,  Y10T29/42

Abstract: A heated capacitor runs current through either a lower metal plate, an upper metal plate, a lower metal trace that lies adjacent to a lower metal plate, an upper metal trace that lies adjacent to an upper metal plate, or both a lower metal trace that lies adjacent to a lower metal plate and an upper metal trace that lies adjacent to an upper metal plate to generate heat from the resistance to remove moisture from a moisture-sensitive insulating layer.

公开(公告)号：US09299697B2

公开(公告)日：2016-03-29

申请号：US14277851

申请日：2014-05-15

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Thomas D. Bonifield ,  Byron Lovell Williams

IPC: H01L27/06 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L49/02 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L28/91 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823481 ,  H01L27/0629 ,  H01L28/40 ,  H01L28/60 ,  H01L29/0692 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/7833

Abstract: A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.

Abstract translation: 微电子器件包含具有高电压节点和低电压节点的高电压分量。 高电压节点通过微电子器件的基板的表面处的高压节点和低电压元件之间的主电介质与低电压节点隔离。 低压隙电介质层设置在高电压节点和主电介质之间。 低带隙电介质层含有至少一个带隙能量小于主电介质带隙能量的子层。 低带隙电介质层围绕高压节点连续延伸超过高压节点。 较低带隙电介质层具有围绕高电压节点的隔离断裂，距离高压节点的至少两倍于低带隙电介质层的厚度。

公开(公告)号：US20150187488A1

公开(公告)日：2015-07-02

申请号：US14576708

申请日：2014-12-19

Applicant: Texas Instruments Incorporated

Inventor： Byron Lovell Williams ,  Asad Mahmood Haider ,  Licheng M. Han

IPC: H01F27/30 ,  H05K3/06 ,  H01F41/04 ,  H01F27/24 ,  H01F27/28

CPC classification number: H05K3/061 ,  H01F5/00 ,  H01F17/0033 ,  H01F41/046 ,  Y10T29/49073

Abstract: An integrated circuit with a micro inductor or with a micro transformer with a magnetic core. A process of forming an integrated circuit with a micro inductor with a magnetic core. A process of forming an integrated circuit with a micro transformer with a magnetic core.

Abstract translation: 具有微电感器或带有磁芯的微型变压器的集成电路。 用具有磁芯的微电感器形成集成电路的工艺。 用具有磁芯的微型变压器形成集成电路的过程。

公开(公告)号：US08754741B2

公开(公告)日：2014-06-17

申请号：US13655419

申请日：2012-10-18

Applicant: Texas Instruments Incorporated

Inventor： Byron Lovell Williams ,  John Britton Robbins

IPC: H01C1/012 ,  H01C7/00 ,  H01C17/075 ,  H01C7/06 ,  H01L27/08 ,  H01L23/525

CPC classification number: H01C7/006 ,  H01C7/06 ,  H01C17/075 ,  H01L23/5228 ,  H01L23/5258 ,  H01L23/647 ,  H01L27/0802 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The resistance of a thin-film resistor is substantially increased by forming the thin-film resistor to line one or more non-conductive trenches. By lining the one or more non-conductive trenches, the overall length of the resistor is increased while still consuming approximately the same surface area as a conventional resistor.

Abstract translation: 薄膜电阻器的电阻通过将薄膜电阻器形成为一个或多个非导电沟槽线来实质上增加。 通过衬套一个或多个非导电沟槽，电阻器的总长度增加，同时仍然消耗与常规电阻器大致相同的表面积。