公开(公告)号：US10121891B2

公开(公告)日：2018-11-06

申请号：US15364971

申请日：2016-11-30

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar ,  Henry Litzmann Edwards

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66 ,  H01L27/092

Abstract: RESURF-based dual-gate p-n bimodal conduction laterally diffused metal oxide semiconductors (LDMOS). In an illustrative embodiment, a p-type source is electrically coupled to an n-type drain. A p-type drain is electrically coupled to an n-type source. An n-type layer serves as an n-type conduction channel between the n-type drain and the n-type source. A p-type top layer is disposed at the surface of the substrate of said semiconductor device and is disposed above and adjacent to the n-type layer. The p-type top layer serves as a p-type conduction channel between the p-type source and the p-type drain. An n-gate controls current flow in the n-type conduction channel, and a p-gate controls current flow in the p-type conduction channel.

公开(公告)号：US10068903B2

公开(公告)日：2018-09-04

申请号：US14713802

申请日：2015-05-15

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Greg Charles Baldwin

IPC: H01L27/092 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/423 ,  H01L29/775 ,  H01L29/76 ,  H01L29/739 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L29/12 ,  H01L27/15

Abstract: Methods and apparatus for artificial exciton devices. An artificial exciton device includes a semiconductor substrate; at least one well region doped to a first conductivity type in a portion of the semiconductor substrate; a channel region in a central portion of the well region; a cathode region in the well region doped to a second conductivity type; an anode region in the well region doped to the first conductivity type; a first lightly doped drain region disposed between the cathode region and the channel region doped to the first conductivity type; a second lightly doped drain region disposed between the anode region and the channel region doped to the second conductivity type; and a gate structure overlying the channel region, the gate structure comprising a gate dielectric layer lying over the channel region and a gate conductor material overlying the gate dielectric. Methods are disclosed.

公开(公告)号：US09853086B2

公开(公告)日：2017-12-26

申请号：US15350694

申请日：2016-11-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Litzmann Edwards ,  Toan Tran ,  Jeffrey R. Debord ,  Ashesh Parikh ,  Bradley David Sucher

IPC: H01L29/66 ,  H01L27/16 ,  H01L35/04 ,  H01L21/265 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/34 ,  H01L35/32 ,  H01L35/34 ,  H01L27/092

CPC classification number: H01L27/16 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823878 ,  H01L27/0617 ,  H01L27/092 ,  H01L29/34 ,  H01L35/04 ,  H01L35/32 ,  H01L35/34

Abstract: In described examples, an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.

公开(公告)号：US20170200796A1

公开(公告)日：2017-07-13

申请号：US15472438

申请日：2017-03-29

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Greg Charles Baldwin

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L29/45 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/266

CPC classification number: H01L27/092 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823475 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/15 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/122 ,  H01L29/41758 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/7391 ,  H01L29/7613 ,  H01L29/775 ,  H01L29/7833 ,  H01L29/7836

Abstract: Methods and apparatus for quantum point contacts. In an arrangement, a quantum point contact device includes at least one well region in a portion of a semiconductor substrate and doped to a first conductivity type; a gate structure disposed on a surface of the semiconductor substrate; the gate structure further comprising a quantum point contact formed in a constricted area, the constricted area having a width and a length arranged so that a maximum dimension is less than a predetermined distance equal to about 35 nanometers; a drain/source region in the well region doped to a second conductivity type opposite the first conductivity type; a source/drain region in the well region doped to the second conductivity type; a first and second lightly doped drain region in the at least one well region. Additional methods and apparatus are disclosed.

公开(公告)号：US09698246B1

公开(公告)日：2017-07-04

申请号：US15257243

申请日：2016-09-06

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  James Robert Todd

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L29/10 ,  H01L29/167 ,  H01L29/06 ,  H01L21/225 ,  H01L21/265 ,  H01L29/423

CPC classification number: H01L29/66681 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823892 ,  H01L27/0928 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/36 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/7818 ,  H01L29/7835

Abstract: A laterally diffused MOS (LDMOS) device includes a substrate having a p-epi layer thereon. A p-body region is in the p-epi layer. An ndrift (NDRIFT) region is within the p-body region providing a drain extension region, and a gate dielectric layer is formed over a channel region in the p-body region adjacent to and on respective sides of a junction with the NDRIFT region, and a patterned gate electrode on the gate dielectric. A DWELL region is within the p-body region, sidewall spacers are on sidewalls of the gate electrode, a source region is within the DWELL region, and a drain region is within the NDRIFT region. The p-body region includes a portion being at least one 0.5 μm wide that has a net p-type doping level above a doping level of the p-epi layer and a net p-type doping profile gradient of at least 5/μm.

公开(公告)号：US20170077294A1

公开(公告)日：2017-03-16

申请号：US15363072

申请日：2016-11-29

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards

IPC: H01L29/78 ,  H01L27/088 ,  H01L23/528 ,  H01L29/417 ,  H01L23/522 ,  H01L23/532 ,  H01L29/06

Abstract: A power transistor includes multiple substantially parallel transistor fingers, where each finger includes a conductive source stripe and a conductive drain stripe. The power transistor also includes multiple substantially parallel conductive connection lines, where each conductive connection line connects at least one source stripe to a common source connection or at least one drain stripe to a common drain connection. The conductive connection lines are disposed substantially perpendicular to the transistor fingers. At least one of the source or drain stripes is segmented into multiple portions, where adjacent portions are separated by a cut location having a higher electrical resistance than remaining portions of the at least one segmented source or drain stripe.

Abstract translation: 功率晶体管包括多个基本上平行的晶体管指状物，其中每个指状物包括导电源极条和导电漏极条纹。 功率晶体管还包括多个基本上平行的导电连接线，其中每个导电连接线将至少一个源条连接到公共源连接或至少一个漏极条连接至公共漏极连接。 导电连接线基本上垂直于晶体管指状物设置。 源极或漏极条纹中的至少一个被分割成多个部分，其中相邻部分被具有比所述至少一个分段源极或漏极条纹的剩余部分更高的电阻的切割位置分开。

公开(公告)号：US20160315141A1

公开(公告)日：2016-10-27

申请号：US15175192

申请日：2016-06-07

Applicant: Texas Instruments Incorporated

Inventor： Sameer P. Pendharkar ,  Binghua Hu ,  Henry Litzmann Edwards

IPC: H01L29/06 ,  H01L21/266 ,  H01L21/02 ,  H01L21/74 ,  H01L29/167 ,  H01L21/265 ,  H01L21/225 ,  H01L21/324

CPC classification number: H01L29/0623 ,  H01L21/02164 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/324 ,  H01L21/74 ,  H01L29/0646 ,  H01L29/167 ,  H01L29/456

Abstract: A semiconductor device has an n-type buried layer formed by implanting antimony and/or arsenic into the p-type first epitaxial layer at a high dose and low energy, and implanting phosphorus at a low dose and high energy. A thermal drive process diffuses and activates both the heavy dopants and the phosphorus. The antimony and arsenic do not diffuse significantly, maintaining a narrow profile for a main layer of the buried layer. The phosphorus diffuses to provide a lightly-doped layer several microns thick below the main layer. An epitaxial p-type layer is grown over the buried layer.

Abstract translation: 半导体器件具有通过以高剂量和低能量将锑和/或砷注入p型第一外延层而形成的n型掩埋层，并且以低剂量和高能量注入磷。 热驱动过程扩散并激活重掺杂物和磷。 锑和砷不会显着扩散，保持埋层主层的狭窄轮廓。 磷扩散以提供在主层下面几微米厚的轻掺杂层。 在掩埋层上生长外延p型层。

公开(公告)号：US09461046B1

公开(公告)日：2016-10-04

申请号：US14974951

申请日：2015-12-18

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  James Robert Todd

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8238

CPC classification number: H01L29/66681 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823892 ,  H01L27/0928 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/36 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/7818 ,  H01L29/7835

Abstract: A laterally diffused MOS (LDMOS) device includes a substrate having a p-epi layer thereon. A p-body region is in the p-epi layer. An ndrift (NDRIFT) region is within the p-body region providing a drain extension region, and a gate dielectric layer is formed over a channel region in the p-body region adjacent to and on respective sides of a junction with the NDRIFT region, and a patterned gate electrode on the gate dielectric. A DWELL region is within the p-body region, sidewall spacers are on sidewalls of the gate electrode, a source region is within the DWELL region, and a drain region is within the NDRIFT region. The p-body region includes a portion being at least one 0.5 μm wide that has a net p-type doping level above a doping level of the p-epi layer and a net p-type doping profile gradient of at least 5/μm.

Abstract translation: 横向扩散的MOS（LDMOS）器件包括其上具有p-epi层的衬底。 p体区位于p-epi层。 NDRIFT区域在提供漏极延伸区域的p体区域内部，并且栅极电介质层形成在与NDRIFT区域的结的相邻侧和相对侧的p体区域的沟道区域上方， 以及栅极电介质上的图案化栅电极。 DWELL区域在p体区域内，侧壁间隔物位于栅电极的侧壁上，源区域在DWELL区域内，漏区在NDRIFT区域内。 p体区域包括至少0.5μm宽的部分，其具有高于p-epi层的掺杂水平的净p型掺杂水平和至少5微米的净p型掺杂分布梯度。

公开(公告)号：US20160260711A1

公开(公告)日：2016-09-08

申请号：US15156590

申请日：2016-05-17

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/417 ,  H01L29/45 ,  H01L27/02 ,  H01L21/8222

CPC classification number: H01L27/0664 ,  H01L21/8222 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/067 ,  H01L29/0649 ,  H01L29/41708 ,  H01L29/45

Abstract: A transistor includes an emitter of a first conductivity type, base of a second conductivity type, collector of the first conductivity type, and cathode of a lateral suppression diode. The emitter is disposed at a top surface of the transistor and configured to receive electrical current from an external source. The base is configured to conduct the electrical current from the collector to the emitter. The base is disposed at the top surface of the transistor and laterally between the emitter and the collector. The collector is configured to attract and collect minority carriers from the base. The cathode of the first conductivity type is surrounded by the base and disposed between the emitter and the collector, and the cathode is configured to suppress a lateral flow of the minority carriers from the base to the collector.

Abstract translation: 晶体管包括第一导电类型的发射极，第二导电类型的基极，第一导电类型的集电极和横向抑制二极管的阴极。 发射极设置在晶体管的顶表面并被配置为从外部源接收电流。 基座被配置为将电流从集电器传导到发射极。 基极设置在晶体管的顶表面，并且在发射极和集电极之间。 收集器被配置为从基地吸引和收集少数载体。 第一导电类型的阴极由基极围绕并且设置在发射极和集电极之间，并且阴极被配置为抑制少数载流子从基极到集电极的横向流动。

公开(公告)号：US09431286B1

公开(公告)日：2016-08-30

申请号：US14555209

申请日：2014-11-26

Applicant: Texas Instruments Incorporated

Inventor： Sameer P Pendharkar ,  Binghua Hu ,  Abbas Ali ,  Henry Litzmann Edwards ,  John P. Erdeljac ,  Britton Robbins ,  Jarvis Benjamin Jacobs

IPC: H01L21/76 ,  H01L21/761 ,  H01L29/06 ,  H01L21/263

CPC classification number: H01L21/761 ,  H01L21/263 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/76286 ,  H01L29/0646

Abstract: A semiconductor device with a buried layer has a deep trench structure abutting the buried layer and a self-aligned sinker along sidewalls of the deep trench structure. The semiconductor device may be formed by forming a portion of a deep trench down to the buried layer, and implanting dopants into a substrate of the semiconductor device along sidewalls of the deep trench, and subsequently forming a remainder of the deep trench extending below the buried layer. Alternatively, the semiconductor device may be formed by forming the deep trench to extend below the buried layer, and subsequently implanting dopants into the substrate of the semiconductor device along sidewalls of the deep trench.

Abstract translation: 具有埋层的半导体器件具有邻近掩埋层的深沟槽结构和沿着深沟槽结构的侧壁的自对准沉降片。 半导体器件可以通过将深沟槽的一部分向下形成到掩埋层上，并且通过深沟槽的侧壁将掺杂剂注入到半导体器件的衬底中，并且随后形成深埋在沟槽下面的其余部分 层。 或者，半导体器件可以通过形成深沟槽以在掩埋层下方延伸而形成，并且随后沿着深沟槽的侧壁将掺杂剂注入到半导体器件的衬底中。