公开(公告)号：US20220069066A1

公开(公告)日：2022-03-03

申请号：US17007726

申请日：2020-08-31

Applicant: Texas Instruments Incorporated

Inventor： Thomas Dyer Bonifield ,  Jeffrey Alan West ,  Byron Lovell Williams ,  Elizabeth Costner Stewart

IPC: H01L49/02 ,  H01L23/522 ,  H01L27/02

Abstract: A galvanic isolation capacitor device includes a semiconductor substrate and a PMD layer over the semiconductor substrate. The PMD layer has a first thickness. A lower metal plate is over the PMD layer and an ILD layer is on the lower metal plate; the ILD layer has a second thickness. A ratio of the first thickness to the second thickness is between about 1 and 1.55 inclusive. A first upper metal plate over the ILD layer has a first area and a second upper metal plate over the ILD layer has a second area; a ratio of the first area to the second area is greater than about 5. The galvanic isolation capacitor device can be part of a multi-chip module.

公开(公告)号：US10886120B2

公开(公告)日：2021-01-05

申请号：US16542628

申请日：2019-08-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey Alan West ,  Adrian Salinas ,  Elizabeth C. Stewart ,  Dhanoop Varghese ,  Thomas D. Bonifield

IPC: H01L21/02 ,  H01L49/02

Abstract: An integrated circuit a semiconductor substrate includes a device die with includes transistors configured to execute an electrical function. A first interconnect layer of the device die is configured to route electrical signals or power to terminals of the transistors. An interlevel dielectric (ILD) layer is located over the interconnect layer. A metal electrode located over the ILD layer. A dielectric barrier layer is located between the ILD layer and the metal electrode. A scribe seal surrounds the device die. A first opening within the dielectric barrier layer surrounds the metal electrode. Second and third openings within the dielectric barrier layer are located between the first opening and the scribe seal.

公开(公告)号：US20200135841A1

公开(公告)日：2020-04-30

申请号：US16176278

申请日：2018-10-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey Alan West ,  Byron Lovell Williams ,  John Britton Robbins

IPC: H01L49/02 ,  H01L21/027 ,  H01L23/544 ,  G03F7/16 ,  G03F7/20 ,  G03F1/42

Abstract: A method of fabricating an integrated circuit includes applying photoresist to a MESA dielectric layer of a semiconductor structure, to generate a photoresist layer. The method also includes exposing the photoresist layer with a grayscale mask, to generate an exposed photoresist layer. The photoresist exposed layer includes a thick photoresist pattern in a first region, a thin photoresist pattern in a second region where a height of the thin photoresist pattern is less than half a height of the thick photoresist pattern, and a gap region between the thick photoresist pattern and the thin photoresist pattern.

公开(公告)号：US20190074350A1

公开(公告)日：2019-03-07

申请号：US16178065

申请日：2018-11-01

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Thomas D. Bonifield ,  Byron Lovell Williams

IPC: H01L49/02 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L23/522 ,  H01L21/8234 ,  H01L27/06

CPC classification number: H01L28/91 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823481 ,  H01L23/522 ,  H01L23/5225 ,  H01L27/0629 ,  H01L28/00 ,  H01L28/40 ,  H01L28/60 ,  H01L29/0692 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/7833

Abstract: A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.

公开(公告)号：US09768245B2

公开(公告)日：2017-09-19

申请号：US15045449

申请日：2016-02-17

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Thomas D. Bonifield ,  Byron Lovell Williams

IPC: H01L49/02 ,  H01L21/02 ,  H01L29/78 ,  H01L27/06 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L28/91 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823481 ,  H01L27/0629 ,  H01L28/40 ,  H01L28/60 ,  H01L29/0692 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/7833

Abstract: A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.

公开(公告)号：US09741787B2

公开(公告)日：2017-08-22

申请号：US15348698

申请日：2016-11-10

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Thomas D. Bonifield ,  Byron Lovell Williams

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L23/552 ,  H01L23/642 ,  H01L28/40

Abstract: High voltage integrated circuit capacitors are disclosed. In an example arrangement. A capacitor structure includes a semiconductor substrate; a bottom plate having a conductive layer overlying the semiconductor substrate; a capacitor dielectric layer deposited overlying at least a portion of the bottom plate and having a first thickness greater than about 6 um in a first region; a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region having an upper surface with a slope of greater than 5 degrees from a horizontal plane and extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and a top plate conductor formed overlying at least a portion of the capacitor dielectric layer in the first region. Methods and additional apparatus arrangements are disclosed.

公开(公告)号：US09525021B2

公开(公告)日：2016-12-20

申请号：US14933638

申请日：2015-11-05

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Thomas D. Bonifield ,  Byron Lovell Williams

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L23/552 ,  H01L23/642 ,  H01L28/40

Abstract: High voltage integrated circuit capacitors are disclosed. In an example arrangement, A capacitor structure includes a semiconductor substrate; a bottom plate having a conductive layer overlying the semiconductor substrate; a capacitor dielectric layer deposited overlying at least a portion of the bottom plate and having a first thickness greater than about 6 um in a first region; a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region having an upper surface with a slope of greater than 5 degrees from a horizontal plane and extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and a top plate conductor formed overlying at least a portion of the capacitor dielectric layer in the first region. Methods and additional apparatus arrangements are disclosed.

Abstract translation: 公开了高压集成电路电容器。 在示例性布置中，A电容器结构包括半导体衬底; 底板，其具有覆盖在半导体衬底上的导电层; 沉积在所述底板的至少一部分上并且在第一区域中具有大于约6um的第一厚度的电容器电介质层; 在第一区域的边缘处的电容器电介质中的倾斜过渡区域，所述倾斜过渡区域具有从水平面倾斜大于5度的上表面并从电容器电介质的第一区域延伸到第二区域 层，其具有比第一厚度低的第二厚度; 以及形成在所述第一区域中覆盖所述电容器电介质层的至少一部分的顶板导体。 公开了方法和附加装置布置。

公开(公告)号：US20160133690A1

公开(公告)日：2016-05-12

申请号：US14933638

申请日：2015-11-05

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Thomas D. Bonifield ,  Byron Lovell Williams

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L23/552 ,  H01L23/642 ,  H01L28/40

Abstract: High voltage integrated circuit capacitors are disclosed. In an example arrangement, A capacitor structure includes a semiconductor substrate; a bottom plate having a conductive layer overlying the semiconductor substrate; a capacitor dielectric layer deposited overlying at least a portion of the bottom plate and having a first thickness greater than about 6 um in a first region; a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region having an upper surface with a slope of greater than 5 degrees from a horizontal plane and extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and a top plate conductor formed overlying at least a portion of the capacitor dielectric layer in the first region. Methods and additional apparatus arrangements are disclosed.

Abstract translation: 公开了高压集成电路电容器。 在示例性布置中，A电容器结构包括半导体衬底; 底板，其具有覆盖在半导体衬底上的导电层; 沉积在所述底板的至少一部分上并且在第一区域中具有大于约6um的第一厚度的电容器电介质层; 在第一区域的边缘处的电容器电介质中的倾斜过渡区域，所述倾斜过渡区域具有从水平面倾斜大于5度的上表面，并且从第一区域延伸到电容器电介质的第二区域 层，其具有比第一厚度低的第二厚度; 以及形成在所述第一区域中覆盖所述电容器电介质层的至少一部分的顶板导体。 公开了方法和附加装置布置。

公开(公告)号：US20140038359A1

公开(公告)日：2014-02-06

申请号：US14046486

申请日：2013-10-04

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Margaret Simmons-Matthews ,  Raymundo M. Camenforte

IPC: H01L21/78

CPC classification number: H01L21/78 ,  H01L21/563 ,  H01L21/568 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A method of forming stacked die devices includes attaching first semiconductor die onto a wafer to form a reconstituted wafer, and then bonding second semiconductor die onto the first semiconductor die to form a plurality of singulated stacked die devices on the wafer. A support tape is attached to a bottomside of the second semiconductor die. A dicing tape is attached to the wafer. The wafer is laser irradiated before or after attachment of the dicing tape at intended dicing lanes that align with gaps between the first semiconductor die to mechanically weaken the wafer at the intended dicing lanes, but not cut through the wafer. The dicing tape is pulled to cleave the wafer into a plurality of singulated portions to form a plurality of singulated stacked die devices attached to the singulated wafer portions by the dicing tape. The support tape is removed prior to cleaving.

Abstract translation: 一种形成堆叠管芯器件的方法包括将第一半导体管芯附着到晶片上以形成重构的晶片，然后将第二半导体管芯接合到第一半导体管芯上，以在晶片上形成多个单独堆叠的管芯器件。 支撑带附接到第二半导体管芯的底部。 切割胶带附着在晶片上。 在将切割带安装到预定的切割通道之前或之后，将该晶片激光照射，该切割线与第一半导体管芯之间的间隙对准，以在期望的切割通道机械地削弱晶片，但不切割穿过晶片。 将切割带拉动以将晶片切割成多个单个部分，以通过切割带形成附接到单个晶片部分的多个单独堆叠的裸片器件。 在切割之前移除支撑带。

公开(公告)号：US12119373B2

公开(公告)日：2024-10-15

申请号：US18080976

申请日：2022-12-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey Alan West

IPC: H01L21/02 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L28/56

Abstract: A method forms a first voltage node of a high voltage component of a microelectronic device. The method also forms a plurality of dielectric layers. The method also forms a second voltage node of the high voltage component of the microelectronic device in a fourth position such that the plurality of dielectric layers is between the first voltage node and the second voltage node. During the forming a second voltage node step, a portion of a third layer in the plurality of dielectric layers, in a region outwardly positioned relative to the second voltage node, is removed to expose the second layer, in the plurality of dielectric layers, in the region.