公开(公告)号：US07312145B2

公开(公告)日：2007-12-25

申请号：US10502129

申请日：2003-10-22

Applicant: Takeshi Hashimoto

Inventor： Takeshi Hashimoto

IPC: H01L21/4763

CPC classification number: H01L23/49572 ,  H01L23/5387 ,  H01L2924/0002 ,  H05K1/0393 ,  H05K3/0032 ,  H05K3/202 ,  H05K3/22 ,  H05K3/386 ,  H05K2201/0761 ,  H05K2203/0522 ,  H01L2924/00

Abstract: The present invention provides an electronic device having high insulating reliability, in which metal portions of a circuit are not electrically conductive with each other via an adhesive layer even when the electronic device is used in high-temperature low-humidity conditions or high-temperature high-humidity conditions, and provides a production method for the electronic device, and a semiconductor device comprising the electronic device. In the electronic device in which a circuit formed by pattern formation of metal portions is attached via an adhesive layer to an insulating base, the adhesive layer, which contacts adjacent metal portions, is divided. Typically, the electronic device is one of a lead frame having a lead frame fixing tape, a TAB tape, and a flexible printed circuit board.

Abstract translation: 本发明提供一种具有高绝缘可靠性的电子器件，其中电路中的金属部分通过粘合剂层彼此不导电，即使电子器件用于高温低湿条件或高温高 并且提供了一种电子设备的制造方法以及包括该电子设备的半导体器件。 在通过金属部分的图案形成形成的电路经由粘合剂层附着到绝缘基底的电子装置中，与邻接的金属部分接触的粘合剂层被分割。 通常，电子设备是具有引线框架固定带，TAB带和柔性印刷电路板的引线框架之一。

公开(公告)号：US07142476B2

公开(公告)日：2006-11-28

申请号：US11151553

申请日：2005-06-14

Applicant: Takeshi Hashimoto ,  Masayuki Kaneda

Inventor： Takeshi Hashimoto ,  Masayuki Kaneda

IPC: G11C7/00

CPC classification number: G11C11/406 ,  G11C2211/4062

Abstract: A refresh counter circuit generating a row address during refresh operation for the memory device which has a normal area for storing data bits and a parity area for storing parity bits, including; n-stage counter which generates the row address corresponding to an address space of the normal area represented by n bits and the parity area represented by m (m

Abstract translation: 一种在具有用于存储数据位的正常区域和用于存储奇偶校验位的奇偶校验位的存储器件的刷新操作期间产生行地址的刷新计数器电路，包括： n阶计数器产生与由n位表示的正常区的地址空间相对应的行地址和由m（m

公开(公告)号：US20060172590A1

公开(公告)日：2006-08-03

申请号：US11324313

申请日：2006-01-04

Applicant: Shoji Yamada ,  Takeshi Hashimoto

Inventor： Shoji Yamada ,  Takeshi Hashimoto

IPC: H01R12/24

CPC classification number: H01R12/88

Abstract: The present invention aims to provide an electric connector which makes it possible to connect easily, hard to separate and enables to maintain good electric connections. The electric connector of the present invention comprises plural contacts 30 each including a contact point 31 contacting each of the plural terminals and an elastic arm part contiguous to the contact 31 and a housing 40 including a reception recess 41 retaining the one end of the circuit board, and attachment recesses 42 for attaching each of the plural contacts, a cover part 43 being laid down toward a direction of insertion of the circuit board, and a pressure part 44 being contiguous to the cover part 43 and being rotatably disposed opposite to the plural contacts 31, wherein the pressure part 44 protrudes into the reception recess 41 as the cover part 43 is laid down.

Abstract translation: 本发明的目的在于提供一种电连接器，其能够容易地连接，难以分离并且能够保持良好的电连接。 本发明的电连接器包括多个触点30，每个触点30包括接触多个端子中的每一个的触点31和与触点31相邻的弹性臂部分以及包括保持电路板的一端的接收凹部41的壳体40 以及用于安装多个触点中的每一个的安装凹部42，朝向电路板的插入方向被放置的盖部43，以及与盖部43邻接并与多个触点相对旋转地设置的压力部44 触点31，其中当盖部43被放置时，压力部44突出到接收凹部41中。

公开(公告)号：US20060002221A1

公开(公告)日：2006-01-05

申请号：US11151553

申请日：2005-06-14

Applicant: Takeshi Hashimoto ,  Masayuki Kaneda

Inventor： Takeshi Hashimoto ,  Masayuki Kaneda

IPC: G11C7/00

CPC classification number: G11C11/406 ,  G11C2211/4062

Abstract: A refresh counter circuit generating a row address during refresh operation for the memory device which has a normal area for storing data bits and a parity area for storing parity bits, comprising; n-stage counter which generates the row address corresponding to an address space of the normal area represented by n bits and the parity area represented by m (m

Abstract translation: 一种刷新计数器电路，用于在具有用于存储数据位的正常区域和用于存储奇偶校验位的奇偶校验区域的存储器件的刷新操作期间产生行地址，包括： n阶计数器产生与由n位表示的正常区的地址空间相对应的行地址和由m（m

公开(公告)号：US20050286331A1

公开(公告)日：2005-12-29

申请号：US11154625

申请日：2005-06-17

Applicant: Yutaka Ito ,  Takeshi Hashimoto ,  Eiji Yamasaki ,  Shigeo Takeuchi ,  Masayuki Kaneda

Inventor： Yutaka Ito ,  Takeshi Hashimoto ,  Eiji Yamasaki ,  Shigeo Takeuchi ,  Masayuki Kaneda

IPC: G11C7/00 ,  G11C11/406

CPC classification number: G11C11/406 ,  G11C2211/4062 ,  G11C2211/4067

Abstract: Disclosed is a semiconductor memory device including an on-chip ECC circuit and having a data retention mode which includes, in the order of state transition, an encoding state EEST by an error correction circuit in which the error correction circuit carries out calculation of parity bits of data of the memory cells, a burst self-refresh state BSST in which the memory cells are self-refreshed in a burst with a period shorter than in ordinary self-refresh, a power-off state PFST in which an internal power supply circuit is partially turned off, a power-on state PNST in which the internal power supply circuit, partially turned off, is turned on, and a decoding state EDST by the error correction circuit in which the error correction circuit corrects errors of the memory cells. In case a command for exiting from the data retention mode in the encoding state, transition may be made to an idle state IST so that re-entry may be made from the decoding state EDST to the BSST.

Abstract translation: 公开了一种包括片上ECC电路并且具有数据保持模式的半导体存储器件，该数据保持模式按状态转换的顺序包括纠错电路的编码状态EEST，其中纠错电路执行奇偶位的计算 的存储器单元的数据，其中存储器单元以比普通自刷新更短的周期的脉冲串自刷新的脉冲串自刷新状态BSST，电源关闭状态PFST，其中内部电源电路 内部电源电路被部分关断的通电状态PNST和通过纠错电路校正存储单元的错误的纠错电路的解码状态EDST被部分关闭。 在编码状态下从数据保持模式退出的命令的情况下，可以转换到空闲状态IST，以便可以从解码状态EDST到BSST进行重新输入。

公开(公告)号：US20050040804A1

公开(公告)日：2005-02-24

申请号：US10878486

申请日：2004-06-29

Applicant: Takeshi Hashimoto ,  Hiromitsu Kojima

Inventor： Takeshi Hashimoto ,  Hiromitsu Kojima

IPC: H03K19/094 ,  G11C5/14 ,  G11C11/404 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4074 ,  H03K19/0948 ,  G11C5/00

CPC classification number: G11C5/147 ,  G11C11/406 ,  G11C11/4074 ,  G11C2211/4016

Abstract: A plate voltage generation circuit comprises: first and second differential circuits (11a, 11b) supplied with a reference voltage (VREF) and an output voltage (VOUT), respectively; a push-pull output circuit (3), connected to the first and second differential circuits, for generating the output voltage; and first and second dead-band control circuits, connected to the first and second differential circuits, respectively, for changing the width of a dead band of the output voltage in accordance with a high level or a low level of dead-band control signals (Sa, Sb) externally supplied.

Abstract translation: 板电压产生电路包括：分别提供有参考电压（VREF）和输出电压（VOUT）的第一和第二差分电路（11a，11b） 连接到第一和第二差分电路的推挽输出电路（3），用于产生输出电压; 以及分别连接到第一和第二差分电路的第一和第二死区控制电路，用于根据高电平或低电平的死区控制信号来改变输出电压的死区的宽度（ Sa，Sb）。

公开(公告)号：US06306957B1

公开(公告)日：2001-10-23

申请号：US09521776

申请日：2000-03-09

Applicant: Akio Nakano ,  Hiroshi Takei ,  Takeshi Hashimoto ,  Yuuki Sakurai

Inventor： Akio Nakano ,  Hiroshi Takei ,  Takeshi Hashimoto ,  Yuuki Sakurai

IPC: C08K310

CPC classification number: C08L83/04 ,  C08G77/045 ,  C08G77/14 ,  C08G77/18 ,  C08G77/20 ,  C08G77/24 ,  C08G77/70 ,  C08L83/00 ,  C08L2666/54

Abstract: An organopolysiloxane, a hydrolyzable group-bearing methylpolysiloxane, a thermal conductive filler, and a curing agent are blended to form a silicone rubber composition which is minimized in viscosity or plasticity increase and remains effectively moldable and workable even when loaded with a large amount of the thermal conductive filler. It cures into a silicone rubber part having a high thermal conductivity.

Abstract translation: 将有机聚硅氧烷，可水解基团的甲基聚硅氧烷，导热填料和固化剂混合以形成硅橡胶组合物，其在粘度或塑性增加方面最小化，并且即使在加载大量的 导热填料。 它固化成具有高导热性的硅橡胶部件。

公开(公告)号：US06296492B1

公开(公告)日：2001-10-02

申请号：US09820750

申请日：2001-03-30

Applicant: Masaki Fujimoto ,  Shuji Kato ,  Kenji Okura ,  Yoshihisa Inaba ,  Takeshi Hashimoto ,  Narutoshi Hoshino ,  Hiroyuki Tominaga ,  Shinya Sasaki

Inventor： Masaki Fujimoto ,  Shuji Kato ,  Kenji Okura ,  Yoshihisa Inaba ,  Takeshi Hashimoto ,  Narutoshi Hoshino ,  Hiroyuki Tominaga ,  Shinya Sasaki

IPC: H01R1200

CPC classification number: H01R24/50 ,  H01R13/6315 ,  H01R13/745 ,  H01R24/46 ,  H01R2103/00

Abstract: A compact receptacle for mating connection with a complementary coaxial plug connector. The receptacle is in use to be mounted on a mobile phone for switching a signal line from an internal antenna to a vehicle's external antenna when placed on a cradle in a vehicle in mating connection with the plug connector on the cradle. The receptacle has a dielectric mold carrying an outer conductor shield fitted on top of the mold, a single spring member, and a single fixed contact member. The conductor shield includes an electrode socket for connection with an outer conductor tube of the plug. The spring member integrally carries a center electrode for connection with a center conductor post of the plug, and a movable contact which forms a normally-closed switch with a fixed contact on the fixed contact member for the above signal switching.

Abstract translation: 紧凑型插座，用于与互补的同轴插头连接器进行配合连接。 插座被安装在移动电话上，用于当将信号线从内部天线切换到车辆的外部天线时，当放置在与支架上的插头连接器配合的车辆的支架上时。 插座具有承载装配在模具顶部的外部导体屏蔽件的绝缘模具，单个弹簧构件和单个固定接触构件。 导体屏蔽包括用于与插头的外导体管连接的电极插座。 弹簧构件一体地携带用于与插头的中心导体柱连接的中心电极和用于上述信号切换的固定触头上形成具有固定触点的常闭开关的可动触点。

公开(公告)号：US06198179B1

公开(公告)日：2001-03-06

申请号：US09250409

申请日：1999-02-16

Applicant: Shigeki Fukunaga ,  Takeshi Hashimoto ,  Shigeru Tsuji

Inventor： Shigeki Fukunaga ,  Takeshi Hashimoto ,  Shigeru Tsuji

IPC: H02K4100

CPC classification number: H02K41/0356

Abstract: A linear actuator can obtain a roughly fixed load within a stroke range. The linear actuator comprises a fixed element, comprising a yoke and a magnet which is magnetized in the radial direction, and a moving element, comprising an electromagnetic coil and a bobbin which surrounds the magnet. A spring is provided for applying a force acting in opposition to the thrust direction acting on the moving element. A constant load stroke area is provided so that the characteristics of the opposite force of this spring balance the characteristics of the thrust force acting on the moving element. The constant load stroke area is an area where one end of the coil in the stroke direction is located in an outside position from one end of the magnet in the stroke direction, and the other end of the coil in the stroke direction is located in an inside position from both ends of the magnet in the stroke direction.

Abstract translation: 线性致动器可以在行程范围内获得大致固定的负载。 线性致动器包括固定元件，其包括磁轭和沿径向磁化的磁体，以及包括电磁线圈和围绕磁体的线轴的移动元件。 提供弹簧用于施加与作用在移动元件上的推力方向相反的力。 提供恒定的载荷冲程区域，使得该弹簧的相反力的特性平衡作用在移动元件上的推力的特性。 恒定载荷行程区域是行程方向上的线圈的一端位于从行程方向的磁体的一端的外侧位置的区域，线圈的行程方向的另一端位于 从磁铁的两端在行程方向的内侧位置。

公开(公告)号：US06180864B2

公开(公告)日：2001-01-30

申请号：US09311249

申请日：1999-05-13

Applicant: Makoto Furuhashi ,  Takeshi Hashimoto

Inventor： Makoto Furuhashi ,  Takeshi Hashimoto

IPC: G10H700

CPC classification number: G10H7/004 ,  G10H7/002

Abstract: A device to perform tone generation while efficiently using a broad bit width bus and essentially eliminating the delay from the request for tone expression until its expression. An arithmetic processing device that generates tones reads the data all at once from a memory in which tone data is stored. This is set so that the delay time from when there is a request for tone generation until the tone is actually generated and expressed is negligible.

Abstract translation: 一种在有效地使用宽位宽总线的同时执行音调生成的装置，并且基本上消除了从语调表达式直到其表达的请求的延迟。 产生音调的算术处理装置从存储音色数据的存储器一次读取数据。 这被设置为使得从存在对音调生成的请求直到音调被实际生成和表达的延迟时间是可忽略的。