公开(公告)号：US20180233556A1

公开(公告)日：2018-08-16

申请号：US15951966

申请日：2018-04-12

Applicant: United Microelectronics Corp.

Inventor： Chang-Po Hsiung ,  Ping-Hung Chiang ,  Shih-Chieh Pu ,  Chia-Lin Wang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Shih-Yin Hsiao ,  Chih-Chung Wang

IPC: H01L29/06 ,  H01L21/311 ,  H01L27/088 ,  H01L21/762 ,  H01L29/51

CPC classification number: H01L29/0649 ,  H01L21/31111 ,  H01L21/7621 ,  H01L21/76232 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/517

Abstract: A semiconductor device including a substrate and a shallow trench isolation (STI) structure is provided. The substrate has a first voltage area and a second voltage area. A top surface of the substrate in the second voltage area is higher than a top surface of the substrate in the first voltage area, and a trench is defined in the substrate in between the first and second voltage area. The STI structure is located in the substrate within the trench, wherein a first portion of the STI structure is located in the first voltage area, a second portion of the STI structure is located in the second voltage area, and a step height difference exist in between a bottom surface of the first portion of the STI structure in the first voltage area and a bottom surface of the second portion of the STI structure in the second voltage area.

公开(公告)号：US20170207127A1

公开(公告)日：2017-07-20

申请号：US15475097

申请日：2017-03-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li ,  Kuan-Chuan Chen ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/823456 ,  H01L21/28035 ,  H01L21/28088 ,  H01L21/31051 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/45 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a first gate and a second gate. The first gate is disposed on the substrate and includes a first gate insulating layer, a polysilicon layer, a silicide layer and a protective layer stacked with each other on the substrate and a first spacer surrounds the first gate insulating layer, the polysilicon layer, the silicide layer and the protective layer. The second gate is disposed on the substrate and includes a second gate insulating layer, a work function metal layer and a conductive layer stacked with each other on the substrate, and a second spacer surrounds the second gate insulating layer, the work function metal layer and the conductive layer.

公开(公告)号：US20170125297A1

公开(公告)日：2017-05-04

申请号：US14925955

申请日：2015-10-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chung Wang ,  Shih-Yin Hsiao ,  Wen-Fang Lee ,  Nien-Chung Li ,  Shu-Wen Lin

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/3105 ,  H01L27/088 ,  H01L21/321 ,  H01L29/49 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3213

CPC classification number: H01L21/82345 ,  H01L21/28035 ,  H01L21/31051 ,  H01L21/32115 ,  H01L21/32139 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/4916 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7834

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a logic region and high-voltage (HV) region; forming a first gate structure on the logic region and a second gate structure on the HV region; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned hard mask on the HV region; and transforming the first gate structure into a metal gate.

公开(公告)号：US20170110536A1

公开(公告)日：2017-04-20

申请号：US14952877

申请日：2015-11-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Wen-Fang Lee ,  Nien-Chung Li ,  Chih-Chung Wang

IPC: H01L29/06 ,  G06F17/50 ,  H01L23/535 ,  H01L29/78

CPC classification number: H01L29/4238 ,  G06F17/5072 ,  H01L23/535 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836 ,  H01L29/785

Abstract: A metal-oxide-semiconductor transistor includes a substrate, a gate insulating layer disposed on the surface of the substrate layer, a metal gate disposed on the gate insulating layer and having at least one plug hole, at least one dielectric plug disposed in the plug hole, and two diffusion regions disposed at two sides of the metal gate in the substrate. The metal gate is configured to operate under an operation voltage greater than 5 v.

公开(公告)号：US20160358919A1

公开(公告)日：2016-12-08

申请号：US14727875

申请日：2015-06-02

Applicant: United Microelectronics Corp.

Inventor： Kuan-Chuan Chen ,  Chih-Chung Wang ,  Wen-Fang Lee ,  Nien-Chung Li ,  Shih-Yin Hsiao

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/0653 ,  H01L21/28238 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/66568 ,  H01L29/66613

Abstract: A method for forming a high voltage transistor is provided. First, a substrate having a top surface is provided, following by forming a thermal oxide layer on the substrate. At least a part of the thermal oxidation layer is removed to form a recess in the substrate, wherein a bottom surface of the recess is lower than the top surface of the substrate. A gate oxide layer is formed in the recess, then a gate structure is formed on the gate oxide layer. The method further includes forming a source/drain region in the substrate.

Abstract translation: 提供一种用于形成高压晶体管的方法。 首先，提供具有顶面的基板，接着在基板上形成热氧化层。 去除热氧化层的至少一部分以在衬底中形成凹部，其中凹部的底表面低于衬底的顶表面。 在凹部中形成栅极氧化层，然后在栅极氧化物层上形成栅极结构。 该方法还包括在衬底中形成源极/漏极区域。

公开(公告)号：US09431239B1

公开(公告)日：2016-08-30

申请号：US14809278

申请日：2015-07-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chiu-Te Lee ,  Ke-Feng Lin ,  Nien-Chung Li ,  Ching-Nan Hwang ,  Shih-Teng Huang ,  Ming-Yen Liu

IPC: H01L21/02 ,  H01L21/225 ,  H01L21/311 ,  H01L21/283 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/167 ,  H01L29/49 ,  H01L29/423

CPC classification number: H01L21/02238 ,  H01L21/02255 ,  H01L21/2253 ,  H01L21/283 ,  H01L21/31111 ,  H01L21/823462 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/1079 ,  H01L29/167 ,  H01L29/4236 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a doped region in the substrate; forming a thermal oxide layer on the substrate and the doped region; removing the thermal oxide layer to form a first recess; forming an epitaxial layer on the substrate and in the first recess; and forming a gate dielectric layer in the epitaxial layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在衬底中形成掺杂区域; 在衬底和掺杂区上形成热氧化层; 去除热氧化物层以形成第一凹槽; 在所述基板和所述第一凹部中形成外延层; 以及在所述外延层中形成栅极电介质层。