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公开(公告)号：US20190249297A1
公开(公告)日：2019-08-15
申请号：US15919191
申请日：2018-03-12
Inventor： Chih-Chien Liu , Pin-Hong Chen , Tsun-Min Cheng , Yi-Wei Chen
IPC: C23C16/455 , H01L21/768 , H01L23/544 , H01L21/285 , H01L21/321 , C23C16/02 , C23C16/34
Abstract: A semiconductor device includes a substrate, a dielectric layer, a first tungsten layer, an interface layer and a second tungsten layer. The dielectric layer is disposed on the substrate and has a first opening and a second opening larger than the first opening. The first tungsten layer is filled in the first opening and is disposed in the second opening. The second tungsten layer is disposed on the first tungsten layer in the second opening, wherein the second tungsten layer has a grain size gradually increased from a bottom surface to a top surface. The interface layer is disposed between the first tungsten layer and the second tungsten layer, wherein the interface layer comprises a nitrogen containing layer. The present invention further includes a method of forming a semiconductor device.
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公开(公告)号：US10211211B1
公开(公告)日：2019-02-19
申请号：US15830006
申请日：2017-12-04
Inventor： Kai-Jiun Chang , Yi-Wei Chen , Tsun-Min Cheng , Chia-Chen Wu , Pin-Hong Chen , Chih-Chieh Tsai , Tzu-Chieh Chen , Yi-An Huang
IPC: H01L29/423 , H01L29/49 , H01L29/778 , H01L29/45 , H01L21/768 , H01L21/3205 , H01L21/4763 , H01L27/108 , H01L23/532 , H01L21/02 , H01L23/535
Abstract: A method for fabricating a buried word line (BWL) of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a barrier layer in the trench; performing a soaking process to reduce chlorine concentration in the barrier layer; and forming a conductive layer to fill the trench.
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公开(公告)号：US20180350673A1
公开(公告)日：2018-12-06
申请号：US15927106
申请日：2018-03-21
Inventor： Pin-Hong Chen , Chih-Chieh Tsai , Tzu-Chieh Chen , Kai-Jiun Chang , Chia-Chen Wu , Yi-An Huang , Tsun-Min Cheng , Yi-Wei Chen , Wei-Hsin Liu
IPC: H01L21/768 , H01L21/324 , H01L23/532
Abstract: A method of forming a semiconductor structure includes providing a material layer having a recess formed therein. A first tungsten metal layer is formed at a first temperature and fills the recess. An anneal process at a second temperature is then performed, wherein the second temperature is higher than the first temperature.
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公开(公告)号：US20180301458A1
公开(公告)日：2018-10-18
申请号：US15922899
申请日：2018-03-15
Inventor： Pin-Hong Chen , Tsun-Min Cheng , Chih-Chieh Tsai , Tzu-Chieh Chen , Kai-Jiun Chang , Chia-Chen Wu , Yi-An Huang , Yi-Wei Chen , Hsin-Fu Huang , Chi-Mao Hsu , Li-Wei Feng , Ying-Chiao Wang , Chung-Yen Feng
IPC: H01L27/108 , H01L23/532 , H01L23/522 , H01L21/285 , H01L23/528 , H01L21/768
Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).
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公开(公告)号：US09754943B1
公开(公告)日：2017-09-05
申请号：US15272425
申请日：2016-09-21
Inventor： Kai-Jiun Chang , Yi-Wei Chen , Tsun-Min Cheng , Chih-Chieh Tsai , Wei-Hsin Liu , Jui-Min Lee , Chia-Lung Chang
IPC: H01L21/336 , H01L21/8242 , H01L27/108 , H01L23/528 , H01L23/532 , H01L29/06
CPC classification number: H01L27/10808 , H01L23/528 , H01L23/53271 , H01L23/53295 , H01L27/10823 , H01L27/10876
Abstract: A dynamic random access memory (DRAM) device includes a substrate, plural word lines and plural bit lines. The word lines are disposed in the substrate along a first trench extending along a first direction. Each of the word lines includes a multi-composition barrier layer, wherein the multi-composition barrier layer includes TiSixNy with x and y being greater than 0 and the multi-composition barrier layer is silicon-rich at a bottom portion thereof and is nitrogen-rich at a top portion thereof. The bit lines are disposed over the word lines and extended along a second direction across the first direction.
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Patent Agency Ranking
公开(公告)号：US09548268B2
公开(公告)日：2017-01-17
申请号：US14731394
申请日：2015-06-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Chi Huang , Yung-Hung Yen , Hsin-Hsing Chen , Chih-Yueh Li , Tsun-Min Cheng
IPC: H01L23/522 , H01L23/528 , H01L23/532
CPC classification number: H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/53295
Abstract: A semiconductor device includes an opening, a metal nitride layer, a bilayer metal layer and a conductive bulk layer. The opening is disposed in a first dielectric layer. The metal nitride layer is disposed in the opening. The bilayer metal layer is disposed on the metal nitride layer in the opening, where the bilayer metal layer includes a first metal layer and a second metal layer which is disposed on the first metal layer and has a greater metal concentration than that of the first metal layer. The conductive bulk layer is filled in the opening.
Abstract translation: 半导体器件包括开口，金属氮化物层，双层金属层和导电体层。 开口设置在第一电介质层中。 金属氮化物层设置在开口中。 双层金属层设置在开口中的金属氮化物层上，其中双层金属层包括第一金属层和设置在第一金属层上并且具有比第一金属的金属浓度更大的金属浓度的第二金属层 层。 导电体层填充在开口中。
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公开(公告)号：US09412653B2
公开(公告)日：2016-08-09
申请号：US14817227
申请日：2015-08-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jia-Jia Chen , Chi-Mao Hsu , Tsun-Min Cheng , Chun-Ling Lin , Huei-Ru Tsai , Ching-Wei Hsu , Chin-Fu Lin , Hsin-Yu Chen
IPC: H01L21/44 , H01L21/768
CPC classification number: H01L21/76847 , H01L21/76898 , H01L2924/0002 , H01L2924/00
Abstract: A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided.
Abstract translation: 硅通孔结构位于衬底的凹槽中。 贯通硅通孔结构包括阻挡层，缓冲层和导电层。 阻挡层覆盖凹部的表面。 缓冲层覆盖阻挡层。 导电层位于缓冲层上并填充凹槽，其中导电层和缓冲层之间的接触表面比缓冲层和阻挡层之间的接触表面更平滑。 此外，还提供了形成所述贯穿硅通孔结构的通硅通孔工艺。
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公开(公告)号：US20140346616A1
公开(公告)日：2014-11-27
申请号：US14454727
申请日：2014-08-08
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Min-Chuan Tsai , Hsin-Fu Huang , Chi-Mao Hsu , Chin-Fu Lin , Chien-Hao Chen , Wei-Yu Chen , Chi-Yuan Sun , Ya-Hsueh Hsieh , Tsun-Min Cheng
CPC classification number: H01L29/4966 , H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L29/4958 , H01L29/512 , H01L29/517 , H01L29/66545 , H01L29/78 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor structure includes a work function metal layer, a (work function) metal oxide layer and a main electrode. The work function metal layer is located on a substrate. The (work function) metal oxide layer is located on the work function metal layer. The main electrode is located on the (work function) metal oxide layer. A semiconductor process forming said semiconductor structure is also provided.
Abstract translation: 半导体结构包括功函数金属层，（功函数）金属氧化物层和主电极。 功函数金属层位于基板上。 （功函数）金属氧化物层位于功函数金属层上。 主电极位于（功函数）金属氧化物层上。 还提供了形成所述半导体结构的半导体工艺。
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公开(公告)号：US20140239419A1
公开(公告)日：2014-08-28
申请号：US13778227
申请日：2013-02-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chien-Hao Chen , Hsin-Fu Huang , Chi-Yuan Sun , Min-Chuan Tsai , Wei-Yu Chen , Nien-Ting Ho , Tsun-Min Cheng , Chi-Mao Hsu
IPC: H01L29/423 , H01L29/40
CPC classification number: H01L29/401 , H01L21/28044 , H01L21/28185 , H01L29/4925 , H01L29/51
Abstract: A method of manufacturing a semiconductor device is provided. A silicon substrate is provided, and a gate insulating layer is formed on the silicon substrate. Then, a silicon barrier layer is formed on the gate insulating layer by the physical vapor deposition (PVD) process. Next, a silicon-containing layer is formed on the silicon barrier layer. The silicon barrier layer of the embodiment is a hydrogen-substantial-zero silicon layer, which has a hydrogen concentration of zero substantially.
Abstract translation: 提供一种制造半导体器件的方法。 提供硅衬底，并且在硅衬底上形成栅极绝缘层。 然后，通过物理气相沉积（PVD）工艺在栅极绝缘层上形成硅阻挡层。 接着，在硅阻隔层上形成含硅层。 本实施方式的硅阻隔层是基本上为氢的氢浓度为零的氢 - 实际为零的硅层。
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公开(公告)号：US11799012B2
公开(公告)日：2023-10-24
申请号：US17012088
申请日：2020-09-04
Inventor： Chun-Chieh Chiu , Pin-Hong Chen , Yi-Wei Chen , Tsun-Min Cheng , Chih-Chien Liu , Tzu-Chieh Chen , Chih-Chieh Tsai , Kai-Jiun Chang , Yi-An Huang , Chia-Chen Wu , Tzu-Hao Liu
IPC: H01L29/49 , H01L21/28 , H01L21/02 , H01L21/3213 , H01L29/423 , H10B12/00 , H01L21/285
CPC classification number: H01L29/4941 , H01L21/02532 , H01L21/02592 , H01L21/28052 , H01L21/28061 , H01L21/3213 , H01L29/42372 , H10B12/05 , H10B12/482 , H01L21/28518 , H01L21/28556 , H10B12/30
Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.
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