公开(公告)号：US20170273190A1

公开(公告)日：2017-09-21

申请号：US15256759

申请日：2016-09-06

Applicant: Unimicron Technology Corp.

Inventor： Shih-Lian Cheng

IPC: H05K3/06 ,  H05K3/46

Abstract: A manufacturing method of a circuit board and a stamp are provided. The method includes: forming a circuit pattern and a dielectric layer on a dielectric substrate; forming a conductive via in the dielectric layer; forming a thermal-sensitive adhesive layer on the dielectric layer; forming a photoresist material layer on the thermal-sensitive adhesive layer; imprinting the photoresist material layer using a stamp, wherein a first conductive layer is disposed on the surface of the pressing side of the stamp, a second conductive layer is disposed on the surface of the other portions; applying a current to the stamp; removing the stamp and the photoresist material layer and the thermal-sensitive adhesive layer below the pressing side to form a patterned photoresist layer and thermal-sensitive adhesive layer; forming a patterned metal layer on the region exposed by the patterned photoresist layer; removing the patterned photoresist layer and thermal-sensitive adhesive layer.

公开(公告)号：US20160007472A1

公开(公告)日：2016-01-07

申请号：US14855404

申请日：2015-09-16

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  Tsung-Yuan Chen ,  Shih-Lian Cheng

IPC: H05K3/00 ,  H05K3/42 ,  H05K3/06 ,  H05K3/30

CPC classification number: H05K3/007 ,  H01L23/5389 ,  H01L24/19 ,  H01L2924/12042 ,  H05K1/18 ,  H05K1/183 ,  H05K1/185 ,  H05K3/0011 ,  H05K3/06 ,  H05K3/30 ,  H05K3/423 ,  H05K3/465 ,  H05K2203/0723 ,  H05K2203/1469 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A method of packaging an electrical device including following steps is provided. A circuit board including a substrate and a first conductive pattern is provided. The electrical device having an electrode is disposed on the circuit board. A dielectric layer is formed on the circuit board to cover the electrical device, the electrode and the first conductive pattern, wherein a first caving pattern is foamed in the dielectric layer by the first conductive pattern. The dielectric layer is patterned to form a through hole and a second caving pattern connecting with the through hole and exposing the electrode. A conductive material is filled in the through hole and the second caving pattern to form a conductive via in the through hole and a second conductive pattern in the second caving pattern. The substrate is removed.

Abstract translation: 提供了包括以下步骤的电气设备的包装方法。 提供了包括基板和第一导电图案的电路板。 具有电极的电气装置设置在电路板上。 电介质层形成在电路板上以覆盖电气设备，电极和第一导电图案，其中第一凹陷图案通过第一导电图案在介电层中发泡。 图案化电介质层以形成与通孔连接并暴露电极的通孔和第二凹陷图案。 导电材料填充在通孔和第二凹陷图案中以在通孔中形成导电通孔，并且在第二凹陷图案中填充第二导电图案。 去除衬底。

公开(公告)号：US09161454B2

公开(公告)日：2015-10-13

申请号：US13726230

申请日：2012-12-24

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  Tsung-Yuan Chen ,  Shih-Lian Cheng

IPC: H05K1/16 ,  H05K1/18 ,  H01L23/538 ,  H01L23/00 ,  H05K3/00 ,  H05K3/46

CPC classification number: H05K3/007 ,  H01L23/5389 ,  H01L24/19 ,  H01L2924/12042 ,  H05K1/18 ,  H05K1/183 ,  H05K1/185 ,  H05K3/0011 ,  H05K3/06 ,  H05K3/30 ,  H05K3/423 ,  H05K3/465 ,  H05K2203/0723 ,  H05K2203/1469 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A method of packaging an electrical device including following steps is provided. A circuit board including a substrate and a first conductive pattern is provided. The electrical device having an electrode is disposed on the circuit board. A dielectric layer is formed on the circuit board to cover the electrical device, the electrode and the first conductive pattern, wherein a first caving pattern is formed in the dielectric layer by the first conductive pattern. The dielectric layer is patterned to form a through hole and a second caving pattern connecting with the through hole and exposing the electrode. A conductive material is filled in the through hole and the second caving pattern to form a conductive via in the through hole and a second conductive pattern in the second caving pattern. The substrate is removed. Moreover, the electrical device package structure is also provided.

Abstract translation: 提供了包括以下步骤的电气设备的包装方法。 提供了包括基板和第一导电图案的电路板。 具有电极的电气装置设置在电路板上。 电介质层形成在电路板上以覆盖电气设备，电极和第一导电图案，其中通过第一导电图案在电介质层中形成第一凹陷图案。 图案化电介质层以形成与通孔连接并暴露电极的通孔和第二凹陷图案。 导电材料填充在通孔和第二凹陷图案中以在通孔中形成导电通孔，并且在第二凹陷图案中填充第二导电图案。 去除衬底。 此外，还提供了电气装置封装结构。

公开(公告)号：US20140053400A1

公开(公告)日：2014-02-27

申请号：US14073846

申请日：2013-11-06

Applicant: Unimicron Technology Corp.

Inventor： Tsung-Yuan Chen ,  Shih-Lian Cheng

IPC: H05K3/40 ,  H05K3/10

CPC classification number: H05K3/4038 ,  H01L21/4857 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/83102 ,  H01L2924/12042 ,  H01L2924/15311 ,  H05K3/10 ,  H05K3/3436 ,  H05K3/4644 ,  H05K3/4694 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/014 ,  H01L2924/00

Abstract: A package substrate includes a core layer, a first dielectric layer, a second circuit pattern, a first solder mask and an insulating layer. A first circuit pattern is disposed on a first surface of the core layer. The first dielectric layer covers the first circuit pattern. The second circuit pattern is located on the first dielectric layer and the second circuit pattern includes an interconnection circuit pattern within a chip mounting area. The first solder mask covers a portion of the second circuit pattern outside the chip mounting area. The insulating layer covers the chip mounting area and the interconnection circuit pattern. A plurality of embedded pads are located on an upper surface of the insulating layer.

Abstract translation: 封装基板包括芯层，第一介电层，第二电路图案，第一焊接掩模和绝缘层。 第一电路图案设置在芯层的第一表面上。 第一电介质层覆盖第一电路图案。 第二电路图案位于第一电介质层上，第二电路图案包括在芯片安装区域内的互连电路图案。 第一焊接掩模覆盖芯片安装区域外部的第二电路图案的一部分。 绝缘层覆盖芯片安装区域和互连电路图案。 多个嵌入式焊盘位于绝缘层的上表面上。