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公开(公告)号：US10074725B1
公开(公告)日：2018-09-11
申请号：US15453351
申请日：2017-03-08
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Shih-Min Chou , Yun-Tzu Chang , Wei-Ning Chen , Wei-Ming Hsiao , Chia-Chang Hsu , Kuo-Chih Lai , Yang-Ju Lu , Yen-Chen Chen , Chun-Yao Yang
IPC: H01L29/76 , H01L29/94 , H01L29/423 , H01L29/06 , H01L29/49 , H01L29/51 , H01L21/02 , H01L21/28 , H01L21/762 , H01L27/088 , H01L27/092 , H01L21/8238 , H01L21/8234
Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.
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公开(公告)号：US09755047B2
公开(公告)日：2017-09-05
申请号：US14924532
申请日：2015-10-27
Applicant: United Microelectronics Corp.
Inventor： Pin-Hong Chen , Kuo-Chih Lai , Chia-Chang Hsu , Chun-Chieh Chiu , Li-Han Chen , Min-Chuan Tsai , Kuo-Chin Hung , Wei-Chuan Tsai , Hsin-Fu Huang , Chi-Mao Hsu
IPC: H01L27/088 , H01L29/66 , H01L29/78 , H01L21/285
CPC classification number: H01L29/665 , H01L21/28518 , H01L21/76843 , H01L21/76855 , H01L21/76897 , H01L29/267 , H01L29/45 , H01L29/7845 , H01L29/785
Abstract: A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.
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公开(公告)号：US20150362905A1
公开(公告)日：2015-12-17
申请号：US14457136
申请日：2014-08-12
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： En-Chiuan Liou , Chia-Chang Hsu , Teng-Chin Kuo , Chia-Hung Wang , Tuan-Yen Yu , Yuan-Chi Pai , Chun-Chi Yu
CPC classification number: G03F7/70633 , G03F1/42 , G03F7/70491 , G05B19/188 , G05B2219/45027 , G05B2219/45031
Abstract: A method of correcting an overlay error includes the following steps. First, an overlay mark disposed on a substrate is captured so as to generate overlay mark information. The overlay mark includes at least a pair of first mark patterns and at least a second mark pattern above the first mark patterns. Then, the overlay mark information is calculated to generate an offset value between two first mark patterns and to generate a shift value between the second mark pattern and one of the first mark patterns. Finally, the offset value is used to compensate the shift value so as to generate an amended shift value.
Abstract translation: 校正重叠错误的方法包括以下步骤。 首先，捕获设置在基板上的覆盖标记，以生成重叠标记信息。 覆盖标记包括至少一对第一标记图案和至少第一标记图案上方的第二标记图案。 然后，计算叠加标记信息以产生两个第一标记图案之间的偏移值，并产生第二标记图案与第一标记图案之一之间的偏移值。 最后，偏移值用于补偿偏移值，以产生修正的移位值。
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公开(公告)号：US12245519B2
公开(公告)日：2025-03-04
申请号：US18542791
申请日：2023-12-18
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chia-Chang Hsu , Tang-Chun Weng , Cheng-Yi Lin , Yung-Shen Chen , Chia-Hung Lin
Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.
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公开(公告)号：US20240415026A1
公开(公告)日：2024-12-12
申请号：US18811754
申请日：2024-08-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chia-Chang Hsu , Chen-Yi Weng , Chin-Yang Hsieh , Jing-Yin Jhang
Abstract: A semiconductor device includes a substrate comprising a MTJ region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region, and a metal interconnection on the logic region. Preferably, the MTJ includes a bottom electrode layer having a gradient concentration, a free layer on the bottom electrode layer, and a top electrode layer on the free layer.
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Patent Agency Ranking
公开(公告)号：US12089419B2
公开(公告)日：2024-09-10
申请号：US18304335
申请日：2023-04-20
Applicant: United Microelectronics Corp.
Inventor： Cheng-Yi Lin , Tang Chun Weng , Chia-Chang Hsu , Yung Shen Chen , Chia-Hung Lin
IPC: H10B61/00 , H01L23/522 , H01L23/528 , H10N50/01 , H10N50/80
CPC classification number: H10B61/00 , H01L23/5226 , H01L23/5283 , H10N50/01 , H10N50/80
Abstract: Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.
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公开(公告)号：US20240213172A1
公开(公告)日：2024-06-27
申请号：US18181559
申请日：2023-03-10
Applicant: United Microelectronics Corp.
Inventor： Chia-Chang Hsu
IPC: H01L23/544 , H10B61/00 , H10B63/00
CPC classification number: H01L23/544 , H10B61/00 , H10B63/80 , H01L2223/54426
Abstract: A semiconductor device includes a dielectric layer, a stop layer, a via and a memory device. The dielectric layer is located on a substrate. The stop layer is located on the dielectric layer. The via extends in the stop layer and the dielectric layer. The memory device is disposed on the via and electrically connected to the via.
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公开(公告)号：US20240122078A1
公开(公告)日：2024-04-11
申请号：US18542791
申请日：2023-12-18
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chia-Chang Hsu , Tang-Chun Weng , Cheng-Yi Lin , Yung-Shen Chen , Chia-Hung Lin
Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.
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公开(公告)号：US11895927B2
公开(公告)日：2024-02-06
申请号：US17319106
申请日：2021-05-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chia-Chang Hsu , Tang-Chun Weng , Cheng-Yi Lin , Yung-Shen Chen , Chia-Hung Lin
Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.
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公开(公告)号：US20220376167A1
公开(公告)日：2022-11-24
申请号：US17705372
申请日：2022-03-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-Wei Kuo , Chia-Chang Hsu
Abstract: A semiconductor device includes a substrate, a first magnetic tunnel junction (MTJ) structure, a second MTJ structure, and an interconnection structure. The first MTJ structure, the second MTJ structure, and the interconnection structure are disposed on the substrate. The interconnection structure is located between the first MTJ structure and the second MTJ structure in a first horizontal direction, and the interconnection structure includes a first metal interconnection and a second metal interconnection. The second metal interconnection is disposed on and contacts the first metal interconnection.
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