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    Method of forming a composite spacer to eliminate polysilicon stringers between elements in a pseudo SRAM cell
    44.
    发明授权
    Method of forming a composite spacer to eliminate polysilicon stringers between elements in a pseudo SRAM cell 有权
    形成复合间隔物以消除伪SRAM单元中的元件之间的多晶硅桁条的方法

    公开(公告)号：US06638813B1

    公开(公告)日：2003-10-28

    申请号：US10059825

    申请日：2002-01-29

    Applicant: Kuo-Chyuan Tzeng ,  Chen-Jong Wang ,  Chung-Wei Chang ,  Wen-Chuan Chiang ,  Wen-Cheng Chen ,  Kuo-Ching Huang

    Inventor： Kuo-Chyuan Tzeng ,  Chen-Jong Wang ,  Chung-Wei Chang ,  Wen-Chuan Chiang ,  Wen-Cheng Chen ,  Kuo-Ching Huang

    IPC: H01L218242

    CPC classification number: H01L28/60 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/76232 ,  H01L27/11

    Abstract: A process for forming a composite insulator spacer on the sides of a buried stack capacitor structure, wherein the buried stack capacitor structure is located overlying a portion of an insulator filled, shallow trench isolation (STI) region, has been developed. A thin silicon nitride spacer is first formed on the sides of the completed buried stack capacitor structure, followed by deposition of a silicon oxide layer. An anisotropic dry etch procedure is next employed removing a top portion of the silicon oxide layer, and resulting in a partially defined silicon oxide spacer. A critical wet etch procedure is next used to remove the bottom portion of the silicon oxide layer, defining the final silicon oxide spacer of the composite insulator spacer, now comprised of a silicon oxide spacer on an underlying silicon nitride spacer. The wet etch procedure allows a gradual slope to be created at the composite insulator spacer—STI region interface, reducing the risk of leaving, or forming polysilicon residuals or stringers on the underlying surface, which can occur during definition of a MOSFET gate structure. The elimination of the polysilicon stringers reduces the risk of leakage between SRAM cell elements, such as buried stack capacitor structures, and MOSFET devices.

    Abstract translation: 已经开发了一种用于在掩埋叠层电容器结构的侧面上形成复合绝缘体间隔物的方法，其中埋层叠层电容器结构位于绝缘体填充的浅沟槽隔离（STI）区域的一部分上方。 首先在完成的掩埋堆叠电容器结构的侧面上形成薄的氮化硅间隔物，然后沉积氧化硅层。 接下来，使用各向异性干蚀刻工艺去除氧化硅层的顶部，并产生部分限定的氧化硅间隔物。 接下来使用关键的湿法蚀刻工艺来去除氧化硅层的底部，限定复合绝缘垫片的最终氧化硅隔离物，现在由下面的氮化硅间隔物上的氧化硅间隔物构成。 湿蚀刻工艺允许在复合绝缘体间隔件-ST区域界面处产生逐渐的斜率，从而降低在MOSFET栅极结构的定义期间可能发生的在下表面上的离开风险或形成多晶硅残余物或桁条。 多晶硅桁架的消除降低了诸如掩埋堆叠电容器结构的SRAM单元元件和MOSFET器件之间的泄漏的风险。

    Method of defining a buried stack capacitor structure for a one transistor RAM cell
    45.
    发明授权
    Method of defining a buried stack capacitor structure for a one transistor RAM cell 有权
    定义一个晶体管RAM单元的掩埋堆叠电容器结构的方法

    公开(公告)号：US06420226B1

    公开(公告)日：2002-07-16

    申请号：US10020753

    申请日：2001-12-12

    Applicant: Wen-Cheng Chen ,  Kuo-Ching Huang ,  Chen-Jong Wang ,  Wen-Chuan Chiang

    Inventor： Wen-Cheng Chen ,  Kuo-Ching Huang ,  Chen-Jong Wang ,  Wen-Chuan Chiang

    IPC: H01L218244

    CPC classification number: H01L27/105 ,  H01L27/11 ,  H01L28/91 ,  H01L29/66181

    Abstract: A process for fabricating a buried stack capacitor structure, to be used in a one transistor, RAM cell, has been developed. The process features formation of a self-aligned, ring shaped storage node opening, formed in a top portion of an silicon oxide filled, shallow trench shape, via a selective dry etch procedure. The selective dry etch procedure in combination with subsequent selective wet etch procedures, create bare portions of semiconductor substrate at the junction of the ring shaped storage node opening and the adjacent top surface of semiconductor, allowing a heavily doped region to be created in this region. The presence of the heavily doped region reduces the node to substrate resistance encountered when a storage node structure is formed in the ring shaped storage node structure, as well as on the overlying the heavily doped region.

    Abstract translation: 已经开发了用于单晶体管，RAM单元中的埋层叠层电容器结构的制造工艺。 该方法特征在于通过选择性干法蚀刻工艺形成形成在氧化硅填充的浅沟槽形状的顶部的自对准的环形存储节点开口。 选择性干蚀刻方法与随后的选择性湿法蚀刻程序结合，在环形存储节点开口和相邻的半导体顶表面的接合处产生半导体衬底的裸露部分，允许在该区域中产生重掺杂区域。 当在环形存储节点结构中形成存储节点结构时，以及在重掺杂区域上覆盖时，重掺杂区域的存在将节点与衬底电阻降低。

    Centrifugal fan with ancillary airflow opening
    46.
    发明授权
    Centrifugal fan with ancillary airflow opening 有权
    离心式风扇带辅助气流开口

    公开(公告)号：US09518584B2

    公开(公告)日：2016-12-13

    申请号：US13666889

    申请日：2012-11-01

    Applicant: Wen-Cheng Chen ,  Chih-Jen Liu

    Inventor： Wen-Cheng Chen ,  Chih-Jen Liu

    IPC: F04D17/16 ,  F04D29/42 ,  F04D25/06

    CPC classification number: F04D17/162 ,  F04D25/0613 ,  F04D29/4226

    Abstract: An exemplary centrifugal fan includes a housing and an impeller received in the housing. The housing defines an air inlet and an air outlet thereof. Airflow driven by the impeller flows out of the housing via the air outlet. The housing further defines an opening adjacent to one end of the air outlet. The ambient air out of the centrifugal fan enters the housing via the opening, and flows out of the housing via the air outlet.

    Abstract translation: 示例性的离心式风扇包括容纳在壳体中的壳体和叶轮。 壳体限定空气入口和空气出口。 由叶轮驱动的气流经由出风口流出壳体。 壳体还限定了与空气出口的一端相邻的开口。 离心风机出来的环境空气经由开口进入外壳，并通过出风口流出外壳。

    Housing of cooling fan and method manufacturing of the same
    47.
    发明授权
    Housing of cooling fan and method manufacturing of the same 有权
    冷却风扇外壳及其制造方法

    公开(公告)号：US09115726B2

    公开(公告)日：2015-08-25

    申请号：US13612897

    申请日：2012-09-13

    Applicant: Wen-Cheng Chen

    Inventor： Wen-Cheng Chen

    IPC: F04D29/42 ,  B29C45/14 ,  F04D29/62

    CPC classification number: F04D29/4226 ,  B29C45/14344 ,  F04D29/626

    Abstract: An exemplary housing of a cooling fan includes a metallic base plate and a plastic bear seat. Clasps extend upwardly from the base plate. The bear seat is formed on the base plate via injection process. A bottom end of the bear seat directly contacts the base plate. The clasps are embedded in the bear seat.

    Abstract translation: 冷却风扇的示例性壳体包括金属底板和塑料轴承座。 卡扣从基板向上延伸。 熊座通过注射工艺在基板上形成。 熊座的底端直接接触底板。 扣子嵌在熊座上。

    Reverse connection MTJ cell for STT MRAM
    50.
    发明授权
    Reverse connection MTJ cell for STT MRAM 有权
    用于STT MRAM的反向连接MTJ单元

    公开(公告)号：US08416600B2

    公开(公告)日：2013-04-09

    申请号：US12626092

    申请日：2009-11-25

    Applicant: Chun-Jung Lin ,  Yu-Jen Wang ,  Ya-Chen Kao ,  Wen-Cheng Chen ,  Ming-Te Liu

    Inventor： Chun-Jung Lin ,  Yu-Jen Wang ,  Ya-Chen Kao ,  Wen-Cheng Chen ,  Ming-Te Liu

    IPC: G11C11/00

    CPC classification number: H01L43/08 ,  G11C11/16 ,  G11C11/1659 ,  H01L27/228 ,  H01L43/12

    Abstract: Apparatus and methods are disclosed herein for a reverse-connection STT MTJ element of a MRAM to overcome the source degeneration effect when switching the magnetization of the MTJ element from the parallel to the anti-parallel direction. A memory cell of a MRAM having a reverse-connection MTJ element includes a switching device having a source, a gate, and a drain, and a reverse-connection MTJ device having a free layer, a fixed layer, and an insulator layer interposed between the free layer and the fixed layer. The free layer of the reverse-connection MTJ device is connected to the drain of the switching device and the fixed layer is connected to a bit line (BL). The reverse-connection MTJ device applies the lower IMTJ capability of the memory cell caused by the source degeneration effect to the less stringent IMTJ(AP->P) while preserving the higher IMTJ capability for the more demanding IMTJ(P->AP).

    Abstract translation: 本文公开了用于MRAM的反向连接STT MTJ元件的装置和方法，以在将MTJ元件的磁化从平行方向切换到反平行方向时克服源退化效应。 具有反向连接MTJ元件的MRAM的存储单元包括具有源极，栅极和漏极的开关器件和具有自由层，固定层和绝缘体层的反向连接MTJ器件， 自由层和固定层。 反连接MTJ器件的自由层连接到开关器件的漏极，固定层连接到位线（BL）。 反向连接MTJ设备将由源退化效应引起的存储器单元的较低IMTJ能力应用于较不严格的IMTJ（AP-> P），同时为更苛刻的IMTJ（P-> AP）保持较高的IMTJ能力。

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