公开(公告)号：US07765019B2

公开(公告)日：2010-07-27

申请号：US11318600

申请日：2005-12-28

Applicant: David Sinai

Inventor： David Sinai

IPC: G06F17/00

CPC classification number: G10L19/008 ,  G06F3/162 ,  H03M1/12 ,  H03M1/66 ,  H04B7/2653 ,  H04B7/2659 ,  H04L5/14 ,  H04M1/0202

Abstract: The present invention provides an audio codec for converting digital audio signals to analogue audio signals, the audio codec comprising: two digital audio bus interfaces for coupling to respective digital audio buses; a digital-only signal path between the two digital audio bus interfaces, such that no analogue processing of the audio signals occurs in the digital-only signal path.

Abstract translation: 本发明提供一种用于将数字音频信号转换为模拟音频信号的音频编解码器，该音频编解码器包括：用于耦合到相应的数字音频总线的两个数字音频总线接口; 两个数字音频总线接口之间的仅数字信号路径，使得在仅数字信号路径中不发生音频信号的模拟处理。

公开(公告)号：US07723965B2

公开(公告)日：2010-05-25

申请号：US11892885

申请日：2007-08-28

Applicant: John Paul Lesso ,  John L. Pennock

Inventor： John Paul Lesso ,  John L. Pennock

IPC: G05F1/613 ,  G05F1/40

CPC classification number: H02M3/1582 ,  H02M3/158 ,  H02M3/33561

Abstract: Electrical power from an input voltage supply is converted to first and second output voltages of opposite polarities using a single inductor (L) and only four principal switches (S1, S2, S4, S6). In contrast to known circuits, none of the switches is exposed to voltages greater than the input voltage (V1). In a first type of charging cycle (FIG. 5(a)-(c)), the first output voltage (V2+) is obtained from the input voltage supply through the inductor. In a second type of charging cycle (FIG. 5 (d)-(f)), the second output voltage (V2−) is obtained from the first output voltage via the intermediate step of storing energy in the same inductor as is used in the first type of charging cycle. Auxiliary switches (S7a, S7b) can be operated in wait states between cycles of the first and second type.

Abstract translation: 使用单个电感器（L）和仅四个主开关（S1，S2，S4，S6）将来自输入电压源的电力转换为具有相反极性的第一和第二输出电压。 与已知的电路相比，没有一个开关暴露于大于输入电压（V1）的电压。 在第一种充电周期（图5（a） - （c））中，从通过电感器的输入电压源获得第一输出电压（V2 +）。 在第二种类型的充电周期（图5（d） - （f））中，通过中间步骤从第一输出电压获得第二输出电压（V2-），该中间步骤将能量存储在与 第一种充电周期。 辅助开关（S7a，S7b）可在第一和第二类型的周期之间以等待状态运行。

公开(公告)号：US07683661B2

公开(公告)日：2010-03-23

申请号：US12201893

申请日：2008-08-29

Applicant: David Edwin Johnson

Inventor： David Edwin Johnson

IPC: G06F13/38 ,  G06F1/22 ,  H03M1/66

CPC classification number: G06F1/22

Abstract: A method and associated apparatus for enabling a plurality of functions of an integrated circuit to be controlled on a single pin of the circuit. The method includes the steps of providing each of the functions with a designated periodically recurring sampling instance during which time the status of a signal on the single pin will be considered to relate to the function designated to that sampling instance, and controlling each of the functions according to the status of the signal on the single pin during each of the plurality of functions' corresponding designated sampling instance.

Abstract translation: 一种用于使集成电路的多个功能能够控制在电路的单个引脚上的方法和相关联的装置。 该方法包括以下步骤：为每个功能提供指定的周期性循环采样实例，在此期间单个引脚上的信号的状态将被认为与指定给该采样实例的功能相关，并且控制每个功能 根据在多个功能对应的指定采样实例中的每个中的单个引脚上的信号的状态。

公开(公告)号：US07622984B2

公开(公告)日：2009-11-24

申请号：US12000547

申请日：2007-12-13

Applicant: John P. Lesso ,  John L. Pennock ,  Peter J. Frith

Inventor： John P. Lesso ,  John L. Pennock ,  Peter J. Frith

IPC: G05F1/10 ,  G05F3/02

CPC classification number: H02M3/07 ,  H02M2001/009 ,  H02M2003/071 ,  H02M2003/072

Abstract: A charge pump circuit and associated method and apparatuses for providing a plurality of output voltages using a single flying capacitor. The circuit includes a network of switches that are operable in a number of different states and a controller for operating the switches in a sequence of states so as to generate positive and negative output voltages together spanning a voltage approximately equal to the input voltage and centered on the voltage at the common terminal.

Abstract translation: 一种电荷泵电路及相关方法和装置，用于使用单个飞行电容器提供多个输出电压。 该电路包括可在多个不同状态下操作的开关网络和用于以一系列状态操作开关的控制器，以便将正和负输出电压一起跨越大约等于输入电压的电压并以 公共端的电压。

公开(公告)号：US07583774B2

公开(公告)日：2009-09-01

申请号：US10986994

申请日：2004-11-15

Applicant: Paul Lesso

Inventor： Paul Lesso

IPC: H03D3/18

CPC classification number: H03L7/087 ,  H03L7/197 ,  H04L7/0008 ,  H04L7/005

Abstract: A clock synchronizer, for generating a local clock signal synchronized to a received clock signal, is described and claimed, along with a corresponding clock synchronization method. The clock synchronizer incorporates a reference oscillator providing a reference signal, and a synthesizer circuit arranged to synthesize a local clock signal from the reference signal. The synthesizer circuit comprises a phase-locked-loop circuit, including a phase detector receiving the reference signal, and a controllable divider arranged in a feedback path from a controlled oscillator to the phase detector, the divider being controllable to set a frequency division value N along the path to determine a ratio of the local clock frequency to the reference frequency. The clock synchronizer also incorporates a clock comparison circuit adapted to generate a digital signal indicative of an asynchronism between the local and remote clock signals. A control link is arranged to link the clock comparison circuit to the divider. This link receives the digital signal and provides a control signal to the divider to adjust the frequency division value N according to the digital signal, to alter the local clock frequency and reduce the asynchronism. Preferably, the clock comparison circuit compares the periods of the local and received clock signals.

Abstract translation: 用于产生与所接收的时钟信号同步的本地时钟信号的时钟同步器与相应的时钟同步方法一起被描述和要求保护。 时钟同步器包括提供参考信号的参考振荡器和被配置为从参考信号合成本地时钟信号的合成器电路。 合成器电路包括锁相环电路，包括接收参考信号的相位检测器和布置在从受控振荡器到相位检测器的反馈路径中的可控分频器，分频器可控制以分频值N 沿路径确定本地时钟频率与参考频率的比值。 时钟同步器还包括适于产生指示本地和远程时钟信号之间的异步的数字信号的时钟比较电路。 控制链路被布置成将时钟比较电路链接到分频器。 该链路接收数字信号，并向分频器提供控制信号以根据数字信号调整分频值N，以改变本地时钟频率并减少异步。 优选地，时钟比较电路比较本地和接收的时钟信号的周期。

公开(公告)号：US07567195B2

公开(公告)日：2009-07-28

申请号：US11957271

申请日：2007-12-14

Applicant: Anthony Magrath

Inventor： Anthony Magrath

IPC: H03M1/66

CPC classification number: H03M1/0665 ,  H03M1/74 ,  H03M3/502

Abstract: A digital-to-analog converter having an input for receiving a digital input signal during each time period. A plurality of elements are each adapted to produce an analog output in response to an input, and an encoder selects a number of the elements and applies inputs to the selected elements. An analog output signal is then formed by summing outputs of the plurality of elements. The encoder selects the number of elements based on a value of the digital input signal, and selects the elements in a predetermined order from the plurality of elements, starting from an element determined by the elements selected in an immediately preceding time period, and excluding a temporarily omitted one of the plurality of elements.

Abstract translation: 一种具有用于在每个时间段期间接收数字输入信号的输入的数模转换器。 多个元件各自适于响应于输入而产生模拟输出，并且编码器选择多个元件并将输入应用于所选择的元件。 然后通过对多个元件的输出求和来形成模拟输出信号。 编码器基于数字输入信号的值来选择元素的数量，并且从以前面的时间段中选择的元素确定的元素开始，从多个元素中以预定顺序选择元素，并且不包括 暂时省略多个元素之一。

公开(公告)号：US07508331B2

公开(公告)日：2009-03-24

申请号：US11822565

申请日：2007-07-06

Applicant: Anthony James Magrath

Inventor： Anthony James Magrath

IPC: H03M1/66

CPC classification number: H03M1/0668 ,  H03M1/74 ,  H03M3/502

Abstract: In a dynamic element matching stage of a digital-to-analogue converter, in which a pair of quantizer outputs are generated, and are constrained such that their sum is equal to the parity of a received bit value, steps are taken to improve baseband noise performance. Each of the quantizers has a feedback loop associated with it, and the performance is improved by determining the quantizer outputs based on these loop values, in order to reduce the overall quantization noise. However, during time periods when these loop values are equal, there are two possible pairs of quantizer outputs that could be chosen, without adversely impacting on the overall quantization noise. the quantizer outputs are monitored during such time periods, and steps are taken to control the quantizer outputs during such time periods, in order to ensure that the two possible pairs of quantizer outputs are chosen with equal probability.

Abstract translation: 在数模转换器的动态元件匹配级中，其中产生一对量化器输出并被约束，使得它们的和等于接收的比特值的奇偶性，采取步骤来改善基带噪声 性能。 每个量化器具有与其相关联的反馈回路，并且通过基于这些环路值确定量化器输出来提高性能，以便降低总体量化噪声。 然而，在这些环路值相等的时间段期间，可以选择两个可能的量化器输出对，而不会对整体量化噪声产生不利影响。 在这样的时间段期间监视量化器输出，并且在这样的时间段期间采取步骤来控制量化器输出，以便确保以相等的概率选择两个可能的量化器输出对。

公开(公告)号：US07466831B2

公开(公告)日：2008-12-16

申请号：US11002207

申请日：2004-12-03

Applicant: Anthony J. Magrath

Inventor： Anthony J. Magrath

IPC: H03G5/00

CPC classification number: H04S1/002

Abstract: The present invention relates to audio signal processing such as equalisation and spatial enhancement functions. The present invention provides an audio signal processing circuit arrangement for two audio channels, and which combines spatial enhancement or acoustic mixing (crosstalk) cancelling with graphic equalisation functions. This is achieved with a circuit structure having a reduced filter count compared with known cascaded circuits dedicated to each function. The circuit structure processes the sum and difference signals through separate filters and then recombines them to recover the separate channels (adding and subtracting respectively).

Abstract translation: 本发明涉及诸如均衡和空间增强功能的音频信号处理。 本发明提供了一种用于两个音频信道的音频信号处理电路装置，并且将空间增强或声音混合（串扰）消除与图形均衡功能相结合。 这是通过与专用于每个功能的已知级联电路相比具有减小的滤波器数量的电路结构来实现的。 电路结构通过单独的滤波器处理和信号和差分信号，然后将它们重新组合以恢复单独的通道（分别加减）。

公开(公告)号：US07376778B2

公开(公告)日：2008-05-20

申请号：US11318601

申请日：2005-12-28

Applicant: David Sinai

Inventor： David Sinai

IPC: G06F13/36

CPC classification number: G06F13/4022

Abstract: The present invention provides a digital bus circuit comprising: a bus conductor having two sections each connected to a pass circuit, each bus section being connected to two bus interfaces for respective circuits; at least three of the bus interfaces comprising a tri-state output buffer having a tri-state mode and one or more logic output modes; wherein in a unitary bus mode the tri-state output buffers are arranged such that only one of said output buffers is not in a tri-state mode, and the pass circuit is arranged to substantially couple said bus sections; and wherein in a dual bus mode the tri-state output buffers are arranged such that only one of the output buffers connected to each bus section is not in a tri-state mode, and wherein the pass circuit is arranged to substantially isolate said bus sections.

Abstract translation: 本发明提供了一种数字总线电路，包括：总线导体，其具有两个部分，每个部分连接到通过电路，每个总线部分连接到用于各个电路的两个总线接口; 至少三个总线接口包括具有三态模式和一个或多个逻辑输出模式的三态输出缓冲器; 其中在单一总线模式中，三状态输出缓冲器被布置成使得仅一个所述输出缓冲器不处于三态模式，并且所述通路电路被布置成基本上耦合所述总线段; 并且其中在双总线模式中，三状态输出缓冲器被布置为使得仅连接到每个总线部分的输出缓冲器中的仅一个不处于三态模式，并且其中通路电路被布置为基本上隔离所述总线部分 。

公开(公告)号：US07301347B2

公开(公告)日：2007-11-27

申请号：US11318458

申请日：2005-12-28

Applicant: David Dearn ,  Holger Haiplik

Inventor： David Dearn ,  Holger Haiplik

IPC: G01R31/08 ,  G01R27/08 ,  G01R19/00

CPC classification number: H02M3/156 ,  G01R19/0092

Abstract: A current sensing circuit for sensing the current through a main switch, such as the PMOS or NMOS switches of a switching regulator, is disclosed. The circuit includes a mirror switch, said mirror switch being substantially similar to said main switch but with a smaller aspect ratio, a difference amplifier for ensuring that the voltage across said first leg and across said second leg are substantially equal and thereby to derive from said mirror switch a sensing current nominally equal to a current flowing in said main switch divided by a sensing ratio, a current source for producing a quiescent current in said difference amplifier and a compensatory device for compensating for said quiescent current such that said current sensing circuit can sense currents in the main switch which are smaller than the quiescent current multiplied by the sensing ratio. The compensatory device may be one or two switches essentially similar to the mirror switch.

Abstract translation: 公开了一种用于感测通过主开关的电流的电流感测电路，例如开关调节器的PMOS或NMOS开关。 电路包括镜开关，所述反射镜开关基本上类似于所述主开关，但具有较小的纵横比;差分放大器，用于确保所述第一支腿和所述第二支腿两端的电压基本相等，从而从所述 反射镜将感测电流标称地等于在所述主开关中流动的电流除以感测比，用于在所述差分放大器中产生静态电流的电流源和用于补偿所述静态电流的补偿装置，使得所述电流感测电路可以 主开关中的感测电流小于静态电流乘以感测比。 补偿装置可以是基本上类似于镜子开关的一个或两个开关。