公开(公告)号：US20240203874A1

公开(公告)日：2024-06-20

申请号：US18406162

申请日：2024-01-07

Applicant: iCometrue Company Ltd.

Inventor： Jin-Yuan Lee ,  Mou-Shiung Lin

IPC: H01L23/528 ,  G11C7/10 ,  G11C11/412 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L23/53204 ,  H01L23/5329 ,  H01L24/17 ,  G11C7/106 ,  G11C11/412

Abstract: A chip package includes a first integrated-circuit (IC) chip; a second integrated-circuit (IC) chip over the first integrated-circuit (IC) chip; a connector over the first integrated-circuit (IC) chip and on a same horizontal level as the second integrated-circuit (IC) chip, wherein the connector comprises a substrate over the first integrated-circuit (IC) chip and a plurality of through vias vertically extending through the substrate of the connector; a polymer layer over the first integrated-circuit (IC) chip, wherein the polymer layer has a portion between the second integrated-circuit (IC) chip and connector, wherein the polymer layer has a top surface coplanar with a top surface of the second integrated-circuit (IC) chip, a top surface of the substrate of the connector and a top surface of each of the plurality of through vias; and an interconnection scheme on the top surface of the polymer layer, the top surface of the second integrated-circuit (IC) chip, the top surface of the connector and the top surface of each of the plurality of through vias.

公开(公告)号：US12014985B2

公开(公告)日：2024-06-18

申请号：US18342145

申请日：2023-06-27

Applicant: Samsung Electronics Co., Ltd. ,  AJOU UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION

Inventor： Youngjae Kang ,  SangWoon Lee ,  Joungeun Yoo ,  Duseop Yoon

IPC: H01L23/532 ,  H01L21/285 ,  H01L23/528 ,  H01L29/45

CPC classification number: H01L23/53204 ,  H01L21/2855 ,  H01L23/5283 ,  H01L29/45

Abstract: A semiconductor interconnect and an electrode for semiconductor devices may include a thin film including a multielement compound represented by Formula 1 and having a thickness equal to or less than about 50 nm, a grain size (A) to thickness (B) ratio (A/B) equal to or greater than about 1.2, and a resistivity equal to or less than about 200 μΩ·cm:

Mn+1AXn  Formula 1

In Formula 1, M, A, X, and n are as described in the specification.

公开(公告)号：US12002770B2

公开(公告)日：2024-06-04

申请号：US16787644

申请日：2020-02-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ying-Chih Hsu ,  Wen-Shiang Liao

IPC: H01L23/64 ,  H01L21/56 ,  H01L23/31 ,  H01L23/532 ,  H01L23/538 ,  H01L49/02

CPC classification number: H01L23/645 ,  H01L21/565 ,  H01L23/31 ,  H01L23/53204 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L28/10

Abstract: A package includes first and second redistribution structures, a die, a permalloy structure, a molding material and a plurality of through vias. The first redistribution structure includes a first metal pattern. The die is disposed over the first redistribution structure. The molding material is disposed over the first redistribution structure and surrounds the die and the permalloy structure. The second redistribution structure is disposed over the die, the permalloy structure and the molding material, and includes a second metal pattern. The through vias penetrate the molding material and connects the first metal pattern to the second metal pattern. The permalloy structure includes a first member and a second member isolated from the first member, the first member and the second member are surrounded by the plurality of through vias and sandwiched between the first metal pattern and the second metal pattern. A method for forming a package is also provided.

公开(公告)号：US11749711B2

公开(公告)日：2023-09-05

申请号：US17578757

申请日：2022-01-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Cheng Chen ,  Wei-Li Huang ,  Chien-Chih Kuo ,  Hon-Lin Huang ,  Chin-Yu Ku ,  Chen-Shien Chen

IPC: H01L49/02 ,  H01F41/04 ,  H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L23/532

CPC classification number: H01L28/10 ,  H01F41/046 ,  H01L21/76823 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/53204 ,  H01L24/05 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a magnetic element over the semiconductor substrate. The semiconductor device structure also includes an adhesive element between the magnetic element and the substrate. The adhesive element extends exceeding opposite edges of the magnetic element. The semiconductor device structure further includes an isolation element extending exceeding the opposite edges of the magnetic element. The isolation element partially covers a top surface of the magnetic element. In addition, the semiconductor device structure includes a conductive line over the isolation element.

公开(公告)号：US20230268406A1

公开(公告)日：2023-08-24

申请号：US18306168

申请日：2023-04-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Che CHIANG ,  Ju-Yuan TZENG ,  Chun-Sheng LIANG ,  Chih-Yang YEH ,  Shu-Hui WANG ,  Jeng-Ya David YEH

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/28 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L29/42372 ,  H01L21/7684 ,  H01L21/28088 ,  H01L21/76846 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/53204 ,  H01L29/4966 ,  H01L29/7851 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/165 ,  H01L29/7843

Abstract: A method includes forming a semiconductor fin over a substrate; forming a gate structure over the semiconductor fin, the gate structure comprising: a first metallic layer; a second metallic layer over the first metallic layer, wherein the first metallic layer is a metal compound of a first element and a second element and the second metallic layer is a single-element metal of the second element; and an oxide layer between the first metallic layer and the second metallic layer.

公开(公告)号：US20230154787A1

公开(公告)日：2023-05-18

申请号：US18156470

申请日：2023-01-19

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Songmei Shen ,  Junyi Zhang

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/306

CPC classification number: H01L21/76802 ,  H01L23/528 ,  H01L23/53204 ,  H01L21/76832 ,  H01L21/76831 ,  H01L21/30604

Abstract: A method for manufacturing a semiconductor structure includes the following operations. A support layer and a first dielectric layer that are stacked are formed on the substrate, in which first trenches are formed in the support layer and the first dielectric layer. A first blocking layer covering sidewalls and bottoms of the first trenches and a top surface of the first dielectric layer is formed. The first blocking layer and the first dielectric layer are etched to form etching holes. The first dielectric layer exposed by the etching holes is removed to form cavities. A second blocking layer is formed, which seals the etching holes at the tops of the cavity. Part of the first blocking layer in the first trenches is removed so that the first trenches expose the substrate. Wires are formed in the first trenches.

公开(公告)号：US20180182703A1

公开(公告)日：2018-06-28

申请号：US15905434

申请日：2018-02-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Chih Chiu ,  Ming-Chung Liang

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53204 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (LK) dielectric layer over a substrate; a first conductive feature in the LK dielectric layer, wherein the first conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a first bottom surface contacting the LK dielectric layer; a first dielectric feature along an upper portion of the first sidewall, wherein a length of the first dielectric feature is at least 10 percent less than a length of the first sidewall; and a second dielectric feature along an upper portion of the second sidewall. The interconnect structure may also include a second conductive feature adjacent to the first conductive feature in the LK dielectric layer.

公开(公告)号：US20180082946A1

公开(公告)日：2018-03-22

申请号：US15797539

申请日：2017-10-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lawrence A. Clevenger ,  Roger A. Quon ,  Terry A. Spooner ,  Wei Wang ,  Chih -Chao Yang

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76879 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295

Abstract: Methods of forming vias include nitridizing exposed surfaces of a first layer and an exposed surface of a conductor underlying the first layer to form a layer of nitridation at said exposed surfaces. Material from the layer of nitridation at the exposed surface of the underlying conductor is etched away. The exposed surface of the underlying conductor is etched away to form a recessed area in the underlying conductor after etching away material from the layer of nitridation. A conductive via that forms a conductive contact with the underlying conductor is formed.

公开(公告)号：US20180061748A1

公开(公告)日：2018-03-01

申请号：US15659547

申请日：2017-07-25

Applicant: Samsung Display Co., Ltd.

Inventor： Byoung Yong KIM ,  Jeong Ho Hwang

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/532

CPC classification number: H01L23/49811 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/53204 ,  H01L23/53209 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05644 ,  H01L2224/05666

Abstract: A semiconductor chip, a display device or an electronic device includes a substrate, one or more conductive pads disposed on the substrate, and one or more bumps electrically connected to the one or more conductive pads, in which the one or more bumps includes a metal core, a polymer layer disposed over a surface of the metal core, and a conductive coating layer disposed over a surface of the polymer layer and electrically connected to the one or more conductive pads.

公开(公告)号：US20180025969A1

公开(公告)日：2018-01-25

申请号：US15215544

申请日：2016-07-20

Applicant: International Business Machines Corporation

Inventor： Praneet Adusumilli ,  Alexander Reznicek ,  Oscar van der Straten ,  Chih-Chao Yang

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/53204 ,  H01L21/02697 ,  H01L21/28 ,  H01L21/283 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76865 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L33/48

Abstract: A middle-of-line interconnect structure including copper interconnects and integral copper alloy caps provides effective electromigration resistance. A metal cap layer is deposited on the top surfaces of the interconnects. A post-deposition anneal causes formation of the copper alloy caps from the interconnects and the metal cap layer. Selective removal of unalloyed metal cap layer material provides an interconnect structure free of metal residue on the dielectric material layer separating the interconnects.