公开(公告)号：US20060109794A1

公开(公告)日：2006-05-25

申请号：US11261622

申请日：2005-10-31

Applicant: Peter Muszynski ,  Jussi Jaatinen ,  Jorma Kaikkonen

Inventor： Peter Muszynski ,  Jussi Jaatinen ,  Jorma Kaikkonen

IPC: H04J3/14 ,  H04B7/00

CPC classification number: H04L1/241 ,  H04L1/1812 ,  H04W24/00 ,  H04W88/08

Abstract: There is disclosed a method of testing a network access element configured for demodulating an enhanced dedicated channel, E-DCH, with hybrid automatic repeat request, HARQ, functionality, the method comprising: transmitting E-DCH packets to the network access element; and selectively autonomously retransmitting E-DCH packets to the network access element.

Abstract translation: 公开了一种测试网络接入元件的方法，所述网络接入元件被配置用于利用混合自动重复请求（HARQ）功能来解调增强型专用信道E-DCH，所述方法包括：向网络接入元件发送E-DCH分组; 并且选择性地将E-DCH分组自主地重传到网络接入单元。

公开(公告)号：US20040225932A1

公开(公告)日：2004-11-11

申请号：US10435147

申请日：2003-05-10

Inventor： Sahir S. Hoda ,  Brad F. Bass ,  Nathan D. Zelle ,  Anand V. Kamannavar

IPC: H04L001/24

CPC classification number: H04L1/241

Abstract: In one embodiment, the present invention is directed to a method for inserting errors into data to facilitate validation of an error detection algorithm. The method comprises: receiving a data corruption command for a plurality of bits; determining, from the data corruption command, a plurality of bit fields within the plurality of bits for data corruption; determining a minimum and maximum number of errors for each of the plurality of bit fields; determining a total number of errors to be inserted; inserting the minimum number of errors into each of the plurality of bit fields at random locations; and randomly inserting additional errors into the plurality of bit fields subject to the maximum number of errors until the total number of errors are inserted.

Abstract translation: 在一个实施例中，本发明涉及一种用于将错误插入数据以便于验证错误检测算法的方法。 该方法包括：接收多个比特的数据损坏命令; 从数据损坏命令确定用于数据损坏的多个位内的多个位字段; 确定所述多个位字段中的每一个的最小和最大错误数; 确定要插入的错误的总数; 在随机位置将最小数量的错误插入到多个位字段的每一个中; 并且随机地将附加的错误插入到受到最大错误数量的多个位字段中，直到插入错误的总数为止。

公开(公告)号：US20040030968A1

公开(公告)日：2004-02-12

申请号：US10291078

申请日：2002-11-08

Inventor： Nong Fan ,  Tuan Hoang ,  Hongtao Jiang

IPC: G06F011/00

CPC classification number: H04L1/243 ,  H04L1/203 ,  H04L1/241

Abstract: A test packet generator (225a) within a physical layer device (230) may generate test packets to be communicated over a closed communication path established within the physical layer device (230). The test packets may include a pseudo-random bit sequence. A receiver within the physical layer device (230) may receive at least a portion of the generated test packet. A test packet checker (225b) within the physical layer device may compare at least a portion of the received test packets with at least a portion of the generated test packets in order to determine the bit error rate for the physical layer device. A window counter (225c) within the physical layer device (230) may count at least a portion of a number of bits received within the generated test packets and a number of bits that are in error in at least a portion of the number of bits received. Accordingly, the bit error rate may be calculated based on a ratio of the number of counted bits in error to the number bits counted in the at least a portion of the number of bits received.

Abstract translation: 物理层设备（230）内的测试分组生成器（225a）可以生成要通过建立在物理层设备（230）内的封闭通信路径进行通信的测试分组。 测试分组可以包括伪随机比特序列。 物理层设备（230）内的接收器可以接收生成的测试分组的至少一部分。 物理层设备内的测试分组检查器（225b）可以将所接收的测试分组的至少一部分与生成的测试分组的至少一部分进行比较，以便确定物理层设备的误码率。 物理层设备（230）内的窗口计数器（225c）可以对生成的测试分组内接收的多个比特的数量的至少一部分进行计数，并且在比特数的至少一部分中计数出错误的比特数 收到了 因此，可以基于错误的计数比特数与在所接收的比特数的至少一部分中计数的比特比的比率来计算误码率。

公开(公告)号：US06373819B1

公开(公告)日：2002-04-16

申请号：US09104329

申请日：1998-06-25

Applicant: Peter Carl Birger Lundh

Inventor： Peter Carl Birger Lundh

IPC: G01R3108

CPC classification number: H04L1/241

Abstract: A system for detecting faults in fault detecting hardware designed to detect faults in a data flow comprising a fault generator for deliberately introducing faults in the data flow before it reaches the fault detecting hardware to establish a known background load of faults in the data flow. A fault counter counts actual faults including the deliberately introduced faults. Software analyzes a difference between the known and actual loads of faults.

Abstract translation: 一种用于检测故障检测硬件中的故障的系统，用于检测数据流中的故障，包括故障发生器，用于在到达故障检测硬件之前故意引入数据流中的故障，以建立数据流中已知的故障背景负载。 故障计数器计数实际故障，包括故意引入的故障。 软件分析了已知和实际故障负载之间的差异。

公开(公告)号：US5870211A

公开(公告)日：1999-02-09

申请号：US661463

申请日：1996-06-11

Applicant: Haruo Yoshida

Inventor： Haruo Yoshida

IPC: H04B10/07 ,  H04B3/46 ,  H04B10/2507 ,  H04B10/508 ,  H04B10/532 ,  H04B10/54 ,  H04B10/556 ,  H04B10/58 ,  H04L1/00 ,  H04L1/24 ,  H04B10/08 ,  G06F11/00

CPC classification number: H04L1/242 ,  H04B10/07953 ,  H04B10/0799 ,  H04B10/25077 ,  H04L1/241

Abstract: An error rate measurement system measures a bit error rate of an optical pulse train having a very high frequency and a short pulse width such as an optical soliton signal. The error rate measurement system includes: an electric pulse generator which generates a high repetition rate and short pulse width electric pulse signal; an optical intensity modulator which receives an optical pulse signal transmitted through a transmission path in a communication network and the electric pulse signal from the electric pulse generator wherein the optical intensity modulator detects a non-coincidence signal; a delay circuit for delaying the electric pulse signal such that the electric pulse signal synchronizes with the optical pulse signal from the transmission path at the optical intensity modulator; an opto-electric converter for converting the non-coincidence signal from the optical intensity modulator to an electric signal; and a signal processor which receives the electric signal from the opto-electric converter to determine a bit error rate of the optical pulse signal from the transmission path based on the electric signal.

Abstract translation: 错误率测量系统测量具有非常高频率和短脉冲宽度的光脉冲串的误码率，例如光孤子信号。 错误率测量系统包括：产生高重复率和短脉冲宽脉冲信号的电脉冲发生器; 光强度调制器，其接收通过通信网络中的传输路径传输的光脉冲信号和来自所述电脉冲发生器的电脉冲信号，其中所述光强度调制器检测到非重合信号; 用于延迟电脉冲信号的延迟电路，使得电脉冲信号与来自光强度调制器处的传输路径的光脉冲信号同步; 用于将来自光强度调制器的不一致信号转换为电信号的光电转换器; 以及信号处理器，其接收来自光电转换器的电信号，以基于电信号确定来自传输路径的光脉冲信号的误码率。

公开(公告)号：US5802105A

公开(公告)日：1998-09-01

申请号：US347526

申请日：1994-11-30

Applicant: Edward G. Tiedemann, Jr. ,  Yu-Cheun Jou ,  Lindsay A. Weaver, Jr. ,  Gwain Bayley

Inventor： Edward G. Tiedemann, Jr. ,  Yu-Cheun Jou ,  Lindsay A. Weaver, Jr. ,  Gwain Bayley

IPC: H04L1/00 ,  H04B3/46 ,  H04B7/26 ,  H04B17/00 ,  H04L1/20 ,  H04L1/24 ,  H04L27/00 ,  H04L29/08 ,  H04L29/14

CPC classification number: H04L1/20 ,  H04L1/241 ,  H04L1/242 ,  H04L2027/0034

Abstract: A system and method for testing signal transmission quality within a digital communication system is disclosed herein. The system may be incorporated within a digital cellular communication system in which information is exchanged over spread spectrum communication channels, among a plurality of mobile users, via at least one cell-site. The system contemplates testing a digital communication channel by transmitting a test sequence of digital data over the communication channel. The test sequence of digital data transmitted over the communication channel is received at a receiving station, within which is also generated a replica of the test sequence of digital data. The accuracy of transmission over the communication channel is then determined by comparing the replica of the test sequence of digital data to the test sequence of data received over the communication channel. The system allows the test sequence of digital data to be transmitted at one of a set of known data rates, with the receive station being disposed to identify the data rate associated with each test sequence of digital data. In a preferred implementation transmission of the test sequence involves generating a first plurality of data packets, which collectively comprise the test sequence of digital data. Each data packet is assigned one of a multiplicity of data rates in accordance with a first pseudorandom process, and is then transmitted at the data rate assigned thereto.

Abstract translation: 本文公开了一种用于测试数字通信系统内的信号传输质量的系统和方法。 该系统可以并入到数字蜂窝通信系统中，其中通过至少一个小区站点在多个移动用户之间通过扩频通信信道交换信息。 该系统考虑通过在通信信道上发送数字数据的测试序列来测试数字通信信道。 通过通信信道发送的数字数据的测试序列在接收站处被接收，在接收站中也产生数字数据的测试序列的副本。 然后通过将数字数据的测试序列的副本与通过通信信道接收的数据的测试序列进行比较来确定通信信道上的传输的准确性。 该系统允许数字数据的测试序列以一组已知数据速率中的一种传输，其中接收站被设置为识别与数字数据的每个测试序列相关联的数据速率。 在优选实施例中，测试序列的传输涉及生成第一多个数据分组，其共同地包括数字数据的测试序列。 每个数据分组根据第一伪随机过程分配多个数据速率中的一个，然后以分配给它的数据速率发送。

公开(公告)号：US5726991A

公开(公告)日：1998-03-10

申请号：US545915

申请日：1995-10-20

Applicant: Dao-Long Chen ,  Robert D. Waldron ,  Khanh C. Nguyen

Inventor： Dao-Long Chen ,  Robert D. Waldron ,  Khanh C. Nguyen

IPC: H04L1/24 ,  G06F11/00

CPC classification number: H04L1/242 ,  H04L1/241

Abstract: A data communication method and apparatus includes an integral bit error rate test system. The system is adapted to receive digital data signals to be transmitted over a communication link and includes a transmitter for transmitting the data signals onto the link. A test signal pattern generator generates a determinable pattern of digital bit test signals which are insertable into an input of the transmitter in place of the digital data signals. A receiver is coupled to the link for receiving the bit test signals and for comparing the received pattern of the bit test signals to the determinable pattern. The bit error rate is computed from the number of bit differences between the transmitted test signals and the determinable pattern.

Abstract translation: 一种数据通信方法和装置，包括一个积分误码率测试系统。 该系统适于接收要通过通信链路传输的数字数据信号，并且包括用于将数据信号发送到链路上的发射机。 测试信号模式发生器产生数字比特测试信号的可确定模式，其可插入到发射机的输入端代替数字数据信号。 接收机耦合到链路以用于接收比特测试信号，并将比特测试信号的接收模式与可确定模式进行比较。 误码率是根据发送的测试信号与可确定模式之间的比特差数来计算的。

公开(公告)号：US5282211A

公开(公告)日：1994-01-25

申请号：US776850

申请日：1991-10-15

Applicant: RobertM. Manlick ,  Matthew L. Fichtenbaum

Inventor： RobertM. Manlick ,  Matthew L. Fichtenbaum

IPC: H04L1/00 ,  H04J3/06 ,  H04L1/20 ,  H04L1/24 ,  H04L7/00 ,  H04L25/02 ,  H04L29/02 ,  G06F11/00

CPC classification number: H04L1/242 ,  H04J3/0611 ,  H04L1/241

Abstract: A bit-error-rate detector (20) in a test set (10) for a frame-based communications channel employs a pseudo-random-number generator (46) at the channel's output end that generates a sequence the same as that produced by a pseudo-random-number generator (16) at the input end, but typically with a timing offset. A chain of delay circuits (38, 40, 42, and 44) receives the channel output. Each delay circuit imposes a delay equal to a single frame time and produces a respective output. One such output (CENTER) is normally compared in an XOR gate (52) with the output of the output-end pseudo-random-number generator (46). The XOR gate (52) applies signals indicative of any symbol mismatches to a shift register (88), which forwards them, after a delay, to a bit-error-rate counter (90). At the same time, another XOR GATE (70) compares the output of the channel or of one of the other delay circuits (38, 42, and 44) with the pseudo-random-number-generator output, and a decoder (80) generates a slip-indicating output when a counter (76), which counts the number of consecutive matches that the latter XOR GATE (70) detects, indicates that the output of the channel or other delay circuit (38, 42, or 44) has matched the output-side pseudo-random-number-generator output a number of times in a row indicative of the likelihood of a frame slip. In response, a slip counter (92) is incremented and the shift register (88) cleared to avoid counting as ordinary bit errors mismatches that occurred in the CENTER signal during the matching sequence in the other signal.

Abstract translation: 用于基于帧的通信信道的测试集合（10）中的误码率检测器（20）在信道的输出端采用伪随机数发生器（46），其生成与由 在输入端的伪随机数发生器（16），但通常具有定时偏移。 延迟电路链（38,40,42和44）接收信道输出。 每个延迟电路施加等于单帧时间的延迟并产生相应的输出。 一个这样的输出（CENTER）通常在XOR门（52）与输出端伪随机数发生器（46）的输出进行比较。 异或门（52）将表示任何符号不匹配的信号应用于移位寄存器（88），该移位寄存器在延迟之后将其转发到位错误率计数器（90）。 同时，另一个XOR GATE（70）将通道的输出或其他延迟电路（38,42和44中的一个）的输出与伪随机数产生器输出进行比较，解码器（80） 当对后一种异或门（70）检测到的连续匹配数进行计数的计数器（76）指示信道或其他延迟电路（38,42或44）的输出具有 将输出侧伪随机数生成器输出在一行中表示帧滑动的可能性的次数进行匹配。 作为响应，打滑计数器（92）递增，并且移位寄存器（88）被清除以避免计数，作为在另一个信号中的匹配序列期间在CENTER信号中发生的普通比特错误不匹配。

公开(公告)号：US4985901A

公开(公告)日：1991-01-15

申请号：US368722

申请日：1989-06-21

Applicant: Herve Cohen ,  Jean-Marie Fouillet

Inventor： Herve Cohen ,  Jean-Marie Fouillet

IPC: H04L1/24 ,  H04N17/00

CPC classification number: H04N17/004 ,  H04L1/241

Abstract: A method and a device are provided for giving an indication on the safety margin offered by a digital video signal circulating on a parallel digital video interface in parallel with a clock signal. For that purpose, the process includes: (a) decoding the data signals with the clock signal in unaltered form; (b) decoding the data signals with the clock signal after a predetermined time shift has been introduced between them; (c) comparing data words obtained from the decoding steps (a) and (b); and (d) repeating steps (a)-(c) with a plurality of successive shifts and determining the minimum amount of shift which results in significant differences between the data words decoded with and without time shift.

Abstract translation: 提供了一种方法和装置，用于与并行于时钟信号的并行数字视频接口上循环的数字视频信号提供关于安全裕度的指示。 为此，该过程包括：（a）用未改变形式的时钟信号对数据信号进行解码; （b）在它们之间引入预定的时间移位之后用时钟信号对数据信号进行解码; （c）比较从解码步骤（a）和（b）获得的数据字; 以及（d）以多个连续的移位重复步骤（a） - （c），并且确定最小的移位量，这导致在有和没有时移的情况下解码的数据字之间的显着差异。

公开(公告)号：US4628507A

公开(公告)日：1986-12-09

申请号：US599362

申请日：1984-04-12

Applicant: Susumu Otani

Inventor： Susumu Otani

IPC: H04L1/00 ,  H04L1/24 ,  H04L25/02 ,  H04L27/00 ,  H04L27/18 ,  H04L27/227 ,  H04B17/00 ,  G06F11/00

CPC classification number: H04L27/2275 ,  H04L1/241

Abstract: A bit errror detection circuit for checking the quality of a transmission path by accurately predicting a true bit error rate (BER) despite changes in the operating point of a non-linear element or fluctuations in the level of an input signal. An inputted PSK-modulated carrier wave is separately phase demodulated by a recovered carrier wave and a phase modulated carrier wave. These two phase demodulated PSK-modulated carrier waves are inputted into separate discriminator circuits 412 and 413 having a common discrimination level where the difference between the outputs can be compared by the comparator circuit 409 to predict a true BER.

Abstract translation: 一种误差检测电路，用于通过精确地预测非线性元件的工作点的变化或者输入信号的电平的波动来精确地预测真实误码率（BER）来检查传输路径的质量。 输入的PSK调制载波被恢复的载波和相位调制载波分别相位解调。 这两个相位解调的PSK调制载波被输入到具有共同鉴别电平的分离鉴频器电路412和413中，其中可以通过比较器电路409比较输出之间的差来预测真实BER。