公开(公告)号：US20090014886A1

公开(公告)日：2009-01-15

申请号：US11951274

申请日：2007-12-05

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

IPC: H01L23/522 ,  H01L21/768 ,  H02H9/00

CPC classification number: H01L27/0251 ,  H01L27/10894

Abstract: The invention provides a dynamic random access memory (DRAM) with an electrostatic discharge (ESD) region. The upper portion of the ESD plug is metal, and the lower portion of the ESD plug is polysilicon. This structure may improve the mechanical strength of the ESD region and enhance thermal conductivity from electrostatic discharging. In addition, the contact area between the ESD plugs and the substrate can be reduced without increasing aspect ratio of the ESD plugs. The described structure is completed by a low critical dimension controlled patterned photoresist, such that the processes and equipments are substantially maintained without changing by a wide margin.

Abstract translation: 本发明提供一种具有静电放电（ESD）区域的动态随机存取存储器（DRAM）。 ESD插头的上部是金属，ESD插头的下部是多晶硅。 该结构可以提高ESD区域的机械强度并增强静电放电的导热性。 此外，可以减少ESD插头和基板之间的接触面积，而不增加ESD插头的纵横比。 所描述的结构由低临界尺寸控制的图案化光致抗蚀剂完成，使得工艺和设备基本上保持而不会大幅变化。

公开(公告)号：US20090011557A1

公开(公告)日：2009-01-08

申请号：US11863282

申请日：2007-09-28

Applicant: Mao-Quan Chen ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Mao-Quan Chen ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L21/336

CPC classification number: H01L27/11521

Abstract: A method for manufacturing a flash memory includes providing a substrate with a sacrificial oxide layer, a sacrificial poly-Si layer, a hard mask layer and a trench exposing part of the substrate and filled with an oxide layer, later depositing a oxide layer conformally on the sacrificial oxide layer and the oxide layer, and afterwards removing the oxide layer on the sacrificial oxide layer and on the top of the oxide layer and the sacrificial oxide layer to form a spacer as a STI oxide spacer.

Abstract translation: 一种用于制造闪速存储器的方法包括：提供具有牺牲氧化物层，牺牲多晶硅层，硬掩模层和暴露衬底部分的衬底并填充氧化物层的衬底，然后将氧化物层保形地 牺牲氧化物层和氧化物层，然后去除牺牲氧化物层上和氧化物层和牺牲氧化物层的顶部上的氧化物层，以形成作为STI氧化物间隔物的间隔物。

公开(公告)号：US07205603B2

公开(公告)日：2007-04-17

申请号：US10764037

申请日：2004-01-23

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7881

Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.

公开(公告)号：US06872623B2

公开(公告)日：2005-03-29

申请号：US10395991

申请日：2003-03-24

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L21/28 ,  H01L29/423 ,  H01L21/336

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7881

Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.

Abstract translation: 浮栅及其制造方法。 提供了半导体衬底，其上依次形成有氧化物层，第一导电层和具有开口的图案化硬掩模层。 间隔件形成在开口的侧壁上。 在硬掩模层上形成第二导电层。 将第二导电层平坦化以暴露图案化硬掩模层的表面。 第二导电层的表面被氧化形成氧化物层。 图案化的硬掩模层和氧化物层以及图案化的硬掩模层下面的第一导电层被去除。

公开(公告)号：US06773993B2

公开(公告)日：2004-08-10

申请号：US09880783

申请日：2001-06-15

Applicant: Chi-Hui Lin ,  Chung-Lin Huang ,  Cheng-Chih Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang ,  Cheng-Chih Huang

IPC: H01L21336

CPC classification number: H01L29/42332 ,  H01L21/28273

Abstract: A method for manufacturing a split-gate flash memory cell, comprising the steps of forming an active region on a semiconductor substrate; forming a buffer layer on the semiconductor substrate; forming a first dielectric layer on the buffer layer; removing part of the first dielectric layer; defining an opening; removing the buffer layer within the opening; forming a gate insulating layer and floating gates; forming a source region in the semiconductor substrate; depositing a conformal second dielectric layer on the opening; removing the buffer layer outside the first dielectric layer and the floating gates; and forming an oxide layer and control gates.

公开(公告)号：US06770532B2

公开(公告)日：2004-08-03

申请号：US10435447

申请日：2003-05-09

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L21336

CPC classification number: H01L29/66583 ,  H01L21/28114 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/42376 ,  H01L29/66553 ,  H01L29/6656

Abstract: A method for fabricating a memory unit with T-shaped gate. A semiconductor substrate forming a dielectric layer, a first opening, and a second opening is provided in a CMOS process. A silicate glass spacer is formed on the sidewall of the first opening and is thermally oxidized to form a light doped area under the silicate glass spacer. The silicate glass spacer is removed. An insulating spacer is formed on the sidewall of the first opening. A first spacer is formed on a sidewall of the second opening. N-type conducting spacers are formed respectively on sidewalls of the insulating spacer and the first spacer. Gate dielectric layers are formed respectively in the first opening and the second opening. A P-type conducting layer fills with the first opening and the second opening, and a second spacer is formed on a sidewall of a conducting spacer of the second opening.

Abstract translation: 一种用于制造具有T形门的存储器单元的方法。 在CMOS工艺中提供形成电介质层，第一开口和第二开口的半导体衬底。 硅酸盐玻璃间隔物形成在第一开口的侧壁上，并被热氧化以在硅酸盐玻璃间隔物下面形成光掺杂区域。 去除硅酸盐玻璃间隔物。 绝缘垫片形成在第一开口的侧壁上。 第一间隔件形成在第二开口的侧壁上。 分别在绝缘间隔物和第一间隔物的侧壁上形成N型导电间隔物。 栅电介质层分别形成在第一开口和第二开口中。 P型导电层填充有第一开口和第二开口，并且第二间隔件形成在第二开口的导电间隔件的侧壁上。

公开(公告)号：US06713349B2

公开(公告)日：2004-03-30

申请号：US10426347

申请日：2003-04-30

Applicant: Chi-Hui Lin ,  Chung-Lin Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang

IPC: H01L21336

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A method for fabricating a split gate flash memory cell. First, a substrate having a doped region covered by a first conductive layer is provided. A floating gate and a first insulating layer are successively formed over the substrate on both sides of the first conductive layer. Thereafter, a conformable second insulating layer and a conformable second conductive layer are successively formed on the substrate and the first insulating layer, and then a third insulating layer is formed thereon. The third insulating layer and the second conductive layer are successively etched back to expose the second insulating layer. The third insulating layer is removed using a cap layer formed on the second conductive layer as a mask to form an opening. Finally, the second conductive layer under the opening is removed to form a control gate underlying the cap layer.

Abstract translation: 一种用于制造分离栅闪存单元的方法。 首先，提供具有被第一导电层覆盖的掺杂区域的基板。 在第一导电层的两侧上的衬底上依次形成浮置栅极和第一绝缘层。 此后，在基板和第一绝缘层上依次形成适形的第二绝缘层和适形的第二导电层，然后在其上形成第三绝缘层。 连续蚀刻第三绝缘层和第二导电层以露出第二绝缘层。 使用形成在第二导电层上的盖层作为掩模去除第三绝缘层以形成开口。 最后，除去开口下方的第二导电层以形成位于盖层下面的控制栅。

公开(公告)号：US06649474B1

公开(公告)日：2003-11-18

申请号：US10426331

申请日：2003-04-30

Applicant: Chi-Hui Lin ,  Chung-Lin Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang

IPC: H01L218247

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/66825

Abstract: A method for fabricating a source line of a flash memory cell. First, a substrate covered by a first insulating layer, a first conductive layer, and a second insulating layer successively is provided. Next, the second insulating layer is patterned to form an opening over the substrate and expose the first conductive layer. Next, a first spacer is formed over the sidewall of the lower opening and a second spacer is formed over the sidewall of the upper opening and the first spacer to make the opening has a “T” profile. Next, the exposed first conductive layer under the opening is removed, and a third spacer over the sidewall of the first spacer and the second spacer is formed. Finally, a source region is formed in the substrate under the opening and the opening is filled with a second conductive layer to form a source line.

Abstract translation: 一种用于制造闪存单元的源极线的方法。 首先，设置由第一绝缘层，第一导电层和第二绝缘层覆盖的基板。 接下来，对第二绝缘层进行图案化以在衬底上形成开口，并露出第一导电层。 接下来，在下开口的侧壁上形成第一间隔件，并且在上开口和第一间隔件的侧壁上形成第二间隔件，以使开口具有“T”轮廓。 接下来，去除开口下面露出的第一导电层，并且形成第一间隔物的侧壁上的第三间隔物和第二间隔物。 最后，在开口下方的基板中形成源极区域，并且开口填充有第二导电层以形成源极线。

公开(公告)号：US6100117A

公开(公告)日：2000-08-08

申请号：US62639

申请日：1998-04-20

Applicant: Chung Peng Hao ,  Chung Lin Huang ,  Lee Chung Yuan ,  Pei-Ing Lee ,  Wu Hsiung Chen

Inventor： Chung Peng Hao ,  Chung Lin Huang ,  Lee Chung Yuan ,  Pei-Ing Lee ,  Wu Hsiung Chen

IPC: H01L21/8242 ,  H01L23/525 ,  H01L27/108 ,  H01L21/82

CPC classification number: H01L27/10894 ,  H01L23/5258 ,  H01L27/10897 ,  H01L2924/0002

Abstract: A method for manufacturing DRAM having a redundancy circuit region. The method utilizes a laser beam permeable layer such as a silicon nitride layer to serve as a stop layer in the etching step of the passivation oxide layer. The method removes the conductive layer, serving as the upper electrode of the capacitor, in the redundancy circuit region II. The fuse of the redundancy circuit region II can thereby be easily blown by the laser beam.

Abstract translation: 一种用于制造具有冗余电路区域的DRAM的方法。 该方法在钝化氧化物层的蚀刻步骤中利用诸如氮化硅层的激光束可透过层作为停止层。 该方法在冗余电路区域II中去除用作电容器的上电极的导电层。 因此，冗余电路区域II的熔断体可以容易地被激光束吹制。

公开(公告)号：US20130203232A1

公开(公告)日：2013-08-08

申请号：US13426832

申请日：2012-03-22

Applicant: TZUNG-HAN LEE ,  CHUNG-LIN HUANG ,  RON-FU CHU

Inventor： TZUNG-HAN LEE ,  CHUNG-LIN HUANG ,  RON-FU CHU

IPC: H01L21/768

CPC classification number: H01L27/10894 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

Abstract: A manufacturing method of a random access memory includes the following steps: providing a semiconductor structure having an array region and a peripheral region; forming a plurality of first trenches in the array region, and concurrently, a plurality of second trenches on the peripheral region; forming a polysilicon layer to cover the array region and the peripheral region, and the first and the second trenches are filled up with the polysilicon layer; planarizing the polysilicon layer so the remaining polysilicon layer only resides in the first and the second trenches; forming a conductive layer on the semiconductor structure; patterning the conductive layer to form a plurality of landing pads on the array region, and a plurality of bit line units on the peripheral region; and forming a plurality of capacitor units which is in electrical connection to the landing pads.

Abstract translation: 随机存取存储器的制造方法包括以下步骤：提供具有阵列区域和周边区域的半导体结构; 在阵列区域中形成多个第一沟槽，同时在周边区域上形成多个第二沟槽; 形成多晶硅层以覆盖阵列区域和外围区域，并且第一和第二沟槽被多晶硅层填充; 平坦化多晶硅层，使得剩余的多晶硅层仅驻留在第一和第二沟槽中; 在半导体结构上形成导电层; 图案化导电层以在阵列区域上形成多个着陆焊盘，以及在周边区域上形成多个位线单元; 以及形成与所述着陆焊盘电连接的多个电容器单元。