公开(公告)号：US12211905B2

公开(公告)日：2025-01-28

申请号：US17672138

申请日：2022-02-15

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Kuo-Hui Su

IPC: H01L29/40 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L29/423 ,  H01L29/51

Abstract: A method for preparing a recessed gate structure includes forming a recessed structure, wherein the recessed structure comprises a substrate with the recess extending into the substrate from a topmost surface of the substrate; forming a first functional layer to at least cover a sidewall of a recess of the recessed structure; forming a second functional layer to cover the first functional layer; performing a rapid thermal treatment to form an interfacial layer extending along an interface between the first functional layer and the second functional layer; and forming a conductive feature to fill up the recess.

公开(公告)号：US12205825B2

公开(公告)日：2025-01-21

申请号：US17706792

申请日：2022-03-29

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yu-Kai Lu

IPC: H01L21/311 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/32 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522

Abstract: The present application provides a method of preparing a semiconductor structure. The method includes providing a conductive film; disposing a barrier layer over the conductive film; disposing a first dielectric layer over the barrier layer; disposing a patterned hard mask over the first dielectric layer; and removing a portion of the first dielectric layer exposed through the patterned hard mask, wherein the removal of the portion of the first dielectric layer includes providing a nitrogen plasma to collide with the portion of the first dielectric layer.

公开(公告)号：US20250016995A1

公开(公告)日：2025-01-09

申请号：US18219241

申请日：2023-07-07

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： CHIH-WEI HUANG ,  HSU-CHENG FAN ,  CHIH-YU YEN

IPC: H10B12/00

Abstract: A memory device includes a semiconductor substrate having an active region, and a word line extending across the active region. The memory device also includes a first source/drain region and a second source/drain region disposed in the active region and on opposite sides of the word line. The memory device further includes a bit line contact disposed over and electrically connected to the first source/drain region. The bit line contact has a tapered profile. In addition, the memory device includes a capacitor contact disposed over and electrically connected to the second source/drain region.

公开(公告)号：US20250014824A1

公开(公告)日：2025-01-09

申请号：US18889659

申请日：2024-09-19

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chien-Chung WANG ,  Hsih-Yang CHIU

IPC: H01G4/228 ,  H01G13/00 ,  H01L29/94 ,  H10B12/00

Abstract: A capacitor structure includes a contact layer having first, second, third, fourth and fifth portions arranged from periphery to center, an insulating layer over the contact layer and having an opening exposing the contact layer, a bottom conductive plate in the opening, a dielectric layer conformally on the bottom conductive plate and contacting the second and fourth portions of the contact layer, and a top conductive plate on the dielectric layer. The bottom conductive plate includes first, second and third portions extending along a depth direction of the opening, separated from each other, and contacting the first, third and fifth portions of the contact layer, respectively. The first portion of the bottom conductive plate surrounds the second portion of the bottom conductive plate, and the second portion of the bottom conductive plate surrounds the third portion of the bottom conductive plate.

公开(公告)号：US12193211B2

公开(公告)日：2025-01-07

申请号：US17831593

申请日：2022-06-03

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ying-Cheng Chuang

IPC: H01L27/108 ,  H01L29/66 ,  H01L29/786 ,  H10B12/00

Abstract: A method of manufacturing a semiconductor device is provided. The method includes: providing a substrate; forming a metallization layer on the substrate; forming an upper dielectric layer over the metallization layer; forming a first sacrificial layer and a second sacrificial layer, each of which penetrates the upper dielectric layer and the metallization layer; removing the upper dielectric layer; forming a width controlling structure between the first sacrificial layer and the second sacrificial layer, wherein the width controlling structure defines a recess exposing the metallization layer; forming a protective layer within the recess of the width controlling structure; removing the width controlling structure to expose a portion of the metallization layer; and patterning the metallization layer to form a word line between the first sacrificial layer and the second sacrificial layer.

公开(公告)号：US12191303B2

公开(公告)日：2025-01-07

申请号：US18635399

申请日：2024-04-15

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu

IPC: H01L21/00 ,  H01L21/761 ,  H01L23/528 ,  H01L27/088 ,  H01L23/00

Abstract: A semiconductor device structure including a doped region under an isolation feature is provided. The semiconductor device structure includes a first substrate, a first well region, a first gate structure, a second gate structure, a first doped region, and a first conductive feature. The substrate has a first surface and a second surface opposite to the first surface. The first well region is in the first substrate. The first well region has a first conductive type. The first gate structure is disposed on the second surface. The second gate structure is disposed on the second surface. The first doped region includes a second conductive type different from the first conductive type. The first doped region is disposed between the first gate structure and the second gate structure. The first conductive feature extends between the first surface of the first substrate and the first doped region.

公开(公告)号：US12191258B2

公开(公告)日：2025-01-07

申请号：US17541772

申请日：2021-12-03

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shing-Yih Shih

IPC: H01L23/544 ,  G03F9/00 ,  H01L21/768 ,  H01L23/522

Abstract: The present application discloses a semiconductor device having integral alignment marks with decoupling features and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a dielectric stack positioned on the substrate; two conductive features positioned in the dielectric stack; a decoupling unit positioned in the dielectric stack, between the two second conductive features, and comprising a bottle-shaped cross-sectional profile; and an alignment mark positioned on the decoupling unit. The alignment mark comprises a fluorescence material.

公开(公告)号：US20250006627A1

公开(公告)日：2025-01-02

申请号：US18886056

申请日：2024-09-16

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： TSE-YAO HUANG

IPC: H01L23/522 ,  H01L23/544

Abstract: The present application discloses a semiconductor device with a decoupling unit. The semiconductor device includes a first tier structure including conductive features of positioned over a substrate, and a decoupling unit the first tier structure positioned between the conductive features; a first-tier-alignment mark positioned on the decoupling unit, and including a fluorescence material; a second tier structure positioned on the first tier structure and including conductive features positioned over and deviated from the conductive features of the first tier structure, and a decoupling unit of positioned over the first tier structure, and positioned between the conductive features of the second tier structure; and a second-tier-alignment mark positioned on the decoupling unit of the second tier structure, and including a fluorescence material. The decoupling units include a low-k dielectric material and respectively include a bottle-shaped cross-sectional profile.

公开(公告)号：US12185520B2

公开(公告)日：2024-12-31

申请号：US17582551

申请日：2022-01-24

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ching-Kai Chuang

IPC: H01L27/108 ,  H10B12/00

Abstract: The present application provides a method of manufacturing a memory device. The method includes steps of providing a semiconductor substrate having a fin portion protruding from a surface of the semiconductor substrate; disposing a semiconductive material over the semiconductor substrate and conformal to the fin portion; disposing a conductive material over the semiconductive material; disposing an insulating material over the conductive material; disposing a patterned photoresist over the insulating material; applying an electric field at a first predetermined angle toward a plasma to remove a portion of the insulating material exposed through the patterned photoresist to form an insulating layer, to remove a portion of the conductive material under the portion of the insulating material to form a conductive layer, and to remove a portion of the semiconductive material under the portion of the insulating material to form a semiconductive layer; and removing the patterned photoresist from the insulating layer.

公开(公告)号：US12183778B2

公开(公告)日：2024-12-31

申请号：US17888749

申请日：2022-08-16

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Szu-Yu Hou ,  Li-Han Lin

IPC: H10B12/00 ,  H01L49/02

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate having a first surface, a plurality of layers disposed on the first surface of the substrate. The plurality of layers includes a first nitride layer disposed on the first surface of the substrate, a first silicon-containing layer disposed on the first nitride layer, an intermediate nitride layer disposed on the first silicon-containing layer, a second silicon-containing layer disposed on the intermediate nitride layer, and a second nitride layer disposed on the second silicon-containing layer. In addition, the semiconductor structure includes a trench capacitor penetrating the plurality of layers and in contact with the substrate. The trench capacitor has a first portion having a first lateral surface and a second portion having a second lateral surface, and the first lateral surface has a slope different from that of the second lateral surface.