公开(公告)号：US20250105809A1

公开(公告)日：2025-03-27

申请号：US18428170

申请日：2024-01-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hua Shao ,  Paul Damitio ,  Bharath Karthik Vasan ,  Joel Martin Halbert

IPC: H03F3/45 ,  H03F1/30 ,  H03K17/30

Abstract: An amplifier includes first through sixth transistors. The first transistor is of a first polarity type and has a control terminal and first and second terminals. The second transistor is of a second polarity type and has a control terminal and first and second terminals. The third transistor is of the first polarity type and has a control terminal and first and second terminals. The second terminal of the third transistor is coupled to the first terminal of the second transistor. The fourth transistor is of the second polarity type and has a control terminal and first and second terminals. The first terminal of the fourth transistor is coupled to the second terminal of the second transistor. The fifth transistor has a control terminal coupled to the control terminal of the third transistor. A sixth transistor has a control terminal coupled to the control terminal of the fourth transistor.

公开(公告)号：US20250105735A1

公开(公告)日：2025-03-27

申请号：US18976467

申请日：2024-12-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jian LIANG ,  Yao LU ,  Chen FENG

IPC: H02M3/155

Abstract: A circuit includes a comparator circuit having a first input, a second input, a first output and a second output. The circuit also includes the first input configured to receive an input voltage of a power supply circuit and the second input configured to receive an output voltage of the power supply circuit. Additionally, the circuit includes the first output to provide the larger of the input voltage or the output voltage and the second output to provide a logic low signal responsive to the input voltage being less than the output voltage, and to provide a logic high signal responsive to the input voltage being greater than or equal to the output voltage.

公开(公告)号：US12261654B2

公开(公告)日：2025-03-25

申请号：US18470659

申请日：2023-09-20

Applicant: Texas Instruments Incorporated

Inventor： Il Han Kim ,  Tarkesh Pande ,  Anuj Batra

IPC: H04B3/54

Abstract: Embodiments include methods of powerline communications using a preamble with band extension is provided. A method may include receiving a packet data unit PDU. Bit-level repetition is applied to at least a portion of the PDU to create a repeated portion. Interleaving is performed per a subchannel. Pilot tones are inserted in the interleaved portion. Each data tone is modulated with respect to a nearest one of the inserted pilot tones. The PDU is transmitted over a power line.

公开(公告)号：US12261537B2

公开(公告)日：2025-03-25

申请号：US17872387

申请日：2022-07-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shanguang Xu ,  Hua Tang ,  Zhaofu Zhou ,  Teng Feng ,  Ian L. Bower

IPC: H02M3/335 ,  H02M1/00 ,  H02M3/00

Abstract: In at least one example, an apparatus includes a current sense circuit, an imbalance detector, and a current balancer. The current sense circuit including a first phase input, a second phase input, a first sense output, and a second sense output. The imbalance detector having a detector output, a first detector input, and second detector input. The first detector input is coupled to the first sense output and the second detector input is coupled to the second sense output. The current balancer having a balancer input and a balancer output. The balancer input is coupled to the detector output.

公开(公告)号：US12261141B2

公开(公告)日：2025-03-25

申请号：US17331921

申请日：2021-05-27

Applicant: Texas Instruments Incorporated

Inventor： Manoj Kumar Jain

IPC: H01L21/768 ,  H01L21/56 ,  H01L23/00 ,  H01L23/532

Abstract: An integrated circuit device (100) and method comprising an IC chip (102) having metal interconnect levels (M1-Mn) including a last copper interconnect level (Mn) and a chip-to-package interconnect (110) overlying and connected to the last copper interconnect level (Mn). The chip-to-package interconnect (110) having a via (112) connected to a first element (306a) of the last copper interconnect level (Mn) and a copper conductive structure (118) (e.g., bump copper). The via (112) includes a barrier material (112a) and a tungsten fill layer (112b), the via coupled between the copper conductive structure (118) and the first element (306a).

公开(公告)号：US12259826B2

公开(公告)日：2025-03-25

申请号：US17693581

申请日：2022-03-14

Applicant: Texas Instruments Incorporated

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Michael Hippleheuser

IPC: G06F12/0895 ,  G06F9/30 ,  G06F9/54 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0897 ,  G06F12/1027 ,  G06F12/12 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F12/128 ,  G06F13/16 ,  G06F15/80 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C29/42 ,  G11C29/44

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for multi-banked victim cache with dual datapath. An example cache system includes a storage element that includes banks operable to store data, ports operable to receive memory operations in parallel, wherein each of the memory operations has a respective address, and a plurality of comparators coupled such that each of the comparators is coupled to a respective port of the ports and a respective bank of the banks and is operable to determine whether a respective address of a respective memory operation received by the respective port corresponds to the data stored in the respective bank.

公开(公告)号：US12257921B2

公开(公告)日：2025-03-25

申请号：US18407719

申请日：2024-01-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ariton E. Xhafa ,  Torbjørn Sørby ,  Minghua Fu ,  Jesus Daniel Torres Bardales ,  Ramanuja Vedantham ,  Alexis Justine Burnight ,  Archanaa Santhana Krishnan

IPC: B60L58/10 ,  H04L67/12

Abstract: A vehicular battery management system (BMS) comprises a battery controller, a set of battery cells, a primary network node coupled to the battery controller, and a secondary network node coupled to the set of battery cells. The primary and secondary network nodes are configured to wirelessly communicate with each other using frames that share a common frame format. The frame format includes one or more bits and a status of the one or more bits indicates whether the secondary network node is to communicate with the primary network node on behalf of another secondary network node.

公开(公告)号：US20250096084A1

公开(公告)日：2025-03-20

申请号：US18471223

申请日：2023-09-20

Applicant: Texas Instruments Incorporated

Inventor： Vijaylaxmi Khanolkar ,  Yi Yan

IPC: H01L23/495 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/07

Abstract: A microelectronic device includes a die pad having a first surface and a second, opposite, surface. A first component is directly attached to the first surface of the die pad through a first thermally conductive material. A second component is directly attached to the second surface of the die pad through a second thermally conductive material. At least a portion of the second component overlaps at least a portion of the first component. The microelectronic device further includes a first thermal shunt connecting the die pad to a first lead, and a second thermal shunt connecting the die pad to a second lead. The first thermal shunt is closer to a center of the first component than to a center of the second component. The second thermal shunt is closer to a center of the second component than to a center of the first component.

公开(公告)号：US20250094044A1

公开(公告)日：2025-03-20

申请号：US18963043

申请日：2024-11-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai Chirca ,  Matthew David Pierson ,  David E. Smith ,  Timothy David Anderson

IPC: G06F3/06 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/06 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0846 ,  G06F12/0855 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/10 ,  G06F12/1009 ,  G06F13/12 ,  G06F13/16 ,  G06F13/40 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27

Abstract: Techniques including receiving configuration information for a trigger control channel of the one or more trigger control channels, the configuration information defining a first one or more triggering events, receiving a first memory management command, store the first memory management command, detecting a first one or more triggering events, and triggering the stored first memory management command based on the detected first one or more triggering events.

公开(公告)号：US20250091857A1

公开(公告)日：2025-03-20

申请号：US18961732

申请日：2024-11-27

Applicant: Texas Instruments Incorporated

Inventor： Adam Joseph Fruehling

IPC: B81B3/00 ,  G02B26/08 ,  H01G5/01 ,  H01H1/00

Abstract: Described embodiments include a microelectromechanical system (MEMS) array comprising a first MEMS device that includes a first movable electrostatic plate elastically connected to a first structure, the first movable electrostatic plate having a first mass, a first fixed electrostatic plate, and a first drive circuit having a first drive output coupled to the first fixed electrostatic plate. There is a second MEMS device that includes a second movable electrostatic plate elastically connected to a second structure, the second movable electrostatic plate having a second mass that is different than the first mass, a second fixed electrostatic plate, and a second drive circuit having a second drive output coupled to the second fixed electrostatic plate.