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    RF power amplifier digital gain flattening over multiband frequencies
    54.
    发明授权
    RF power amplifier digital gain flattening over multiband frequencies 有权

    公开(公告)号：US06812789B2

    公开(公告)日：2004-11-02

    申请号：US10197431

    申请日：2002-07-18

    Applicant: Christopher David Mackey ,  Brian Christopher Boorman ,  Thomas Daniel O Brien

    Inventor： Christopher David Mackey ,  Brian Christopher Boorman ,  Thomas Daniel O Brien

    IPC: H03G320

    CPC classification number: H03G1/007

    Abstract: A method and apparatus for maintaining approximately constant gain of an RF power amplifier includes a digital control module for modifying gain parameters of the power amplifier to provide a constant fixed power gain over the entire frequency range of operation. The digital control module compares stored frequency response parameters, which are indicative of the inherent closed-loop gain of the power amplifier, with the current selected gain and carrier frequency setting to generate a digital gain control value. The digital gain control value is used to modify a detected input RF envelope in the power amplifier analog loop. The modified input envelope is compared with an envelope of the transmitted RF signal to adjust the gain of the power amplifier. Optionally, the detected RF input envelope may be sampled to digitally compensate for variations in the RF input signal.

    Folding camper for pickup trucks
    55.
    发明授权
    Folding camper for pickup trucks 失效
    皮卡车折叠露营车

    公开(公告)号：US06679542B1

    公开(公告)日：2004-01-20

    申请号：US10317656

    申请日：2002-12-12

    Applicant: Thomas Daniel Semotuk

    Inventor： Thomas Daniel Semotuk

    IPC: B60P332

    CPC classification number: B60P3/341

    Abstract: A folding camper (15) is provided for a pickup truck (20). A pair of side wings (22) are pivotally attached to a base assembly (10) that rests on the floor of the pickup truck bed. A roof (28) is attached to a roof lifting mechanism (30). Enclosures (32), (38), and (42) enclose the area between base assembly (10) and roof (28) when expanded. Doors (34) and (36) provide access to the interior. Slanted jacks (47) and (48) lift the camper off the pickup truck bed. Straps (62) and braces (64) and (66) stabilize the camper (15). Roof racks (46) are attached to roof (28) for long objects. When closed, side wings (22) are folded upward, and enclosures (32), (38), and (42) are folded inward. Roof (28) is lowered to rest on base assembly (10) and to overlap side wings (22). Lower door (36) is operable and the interior of camper (15) is available for transport or storage use.

    Abstract translation: 为皮卡车（20）提供折叠露营器（15）。 一对侧翼（22）枢转地附接到搁置在皮卡车底盘的底座组件（10）上。 屋顶（28）附接到屋顶提升机构（30）。 当扩展时，外壳（32），（38）和（42）围绕基座组件（10）和屋顶（28）之间的区域。 门（34）和（36）提供进入内部的通道。 倾斜千斤顶（47）和（48）将摄像机从皮卡车上提起。 肩带（62）和支架（64）和（66）稳定露营者（15）。 屋顶架（46）连接到屋顶（28）上用于长物体。 当关闭时，侧翼（22）向上折叠，并且外壳（32），（38）和（42）向内折叠。 屋顶（28）被降下以搁置在基座组件（10）上并与侧翼（22）重叠。 下门（36）是可操作的，并且露营者（15）的内部可用于运输或存储使用。

    Efficient implementation of first-in-first-out memories for multi-processor systems
    56.
    发明授权
    Efficient implementation of first-in-first-out memories for multi-processor systems 有权
    高效地实现多处理器系统的先进先出存储器

    公开(公告)号：US06615296B2

    公开(公告)日：2003-09-02

    申请号：US09881512

    申请日：2001-06-14

    Applicant: Thomas Daniel ,  Anil Gupta

    Inventor： Thomas Daniel ,  Anil Gupta

    IPC: G06F1320

    CPC classification number: G06F15/167

    Abstract: To reduce FIFO access cycles across a system bus in a multi-processor system in which two processors communicate across a system bus through a FIFO, two separate FIFO descriptors are provided. The first descriptor is maintained by the processor located on-board with the FIFO, and the second descriptor is maintained by an off-board processor which communicates with the FIFO across the bus. When one processor performs a FIFO operation, the processor updates the other processor's descriptor via a memory access across the bus. Additionally, one module passes credits to the other to indicate that the latter has permission to perform a plurality of FIFO operations consecutively. In one embodiment a special non-valid data value is used to indicate an empty FIFO position.

    Abstract translation: 为了减少跨处理器系统中的系统总线的FIFO访问周期，在多处理器系统中，两个处理器通过FIFO通过系统总线进行通信，则提供两个独立的FIFO描述符。 第一描述符由位于板上的处理器由FIFO维护，第二描述符由通过总线与FIFO通信的板外处理器来维护。 当一个处理器执行FIFO操作时，处理器通过总线上的存储器访问来更新其他处理器的描述符。 此外，一个模块向另一个模块传递信用以指示后者具有连续执行多个FIFO操作的许可。 在一个实施例中，使用特殊的非有效数据值来指示空的FIFO位置。

    Multi-phase melt cast toilet bar and a method for its manufacture
    57.
    发明授权
    Multi-phase melt cast toilet bar and a method for its manufacture 失效
    多相熔铸马桶条及其制造方法

    公开(公告)号：US06376441B1

    公开(公告)日：2002-04-23

    申请号：US09605063

    申请日：2000-06-28

    Applicant: Michael Edward Ross ,  Thomas Daniel Arkins ,  Robert Alfread Bennett ,  Syed Husain Abbas

    Inventor： Michael Edward Ross ,  Thomas Daniel Arkins ,  Robert Alfread Bennett ,  Syed Husain Abbas

    IPC: A61K750

    CPC classification number: C11D17/006 ,  C11D13/16

    Abstract: A multi-phase melt cast toilet bar which has at least one interface along a plane perpendicular to the plane formed by the x and y-axis of said bar, and a process of making the bar is described. Each phase, containing a cleansing agent, is reproducibly positioned in the bar to be used simultaneously thereby allowing the user to simultaneously derive benefits from the use of the cleansing agents contained in the bar's layers. The process for making the bar is a continuous one, whereby the molten cleansing agents are simultaneously or separately poured into the mold, simultaneously or separately allowed to harden, and where the mold divider is not removed or removed either after hardening of the adjacent molten cleansing agent but before the pouring of the next molten cleansing agent, or removed while at least one phase remains flowable. The hardened multi-phase toilet bar is finally ejected from the mold.

    Abstract translation: 描述了一种多相熔铸马桶杆，其具有沿着垂直于由所述杆的x和y轴形成的平面的平面的至少一个界面，以及制造棒的过程。 含有清洁剂的每个相可再现地定位在棒中以同时使用，从而允许使用者同时从包含在酒吧层中的清洁剂的使用中获益。 制造棒材的方法是连续的，由此熔融清洁剂同时或分别地注入模具中，同时或分开地使其硬化，并且在相邻的熔融清洗物硬化之后，除去或除去模具分隔器 但在注入下一个熔融清洗剂之前，或者在至少一个相保持可流动的同时除去。 硬化的多相马桶杆最终从模具中排出。

    Register reservation method for fast context switching in microprocessors
    58.
    发明授权
    Register reservation method for fast context switching in microprocessors 失效
    微处理器快速上下文切换的注册预约方法

    公开(公告)号：US5987258A

    公开(公告)日：1999-11-16

    申请号：US883137

    申请日：1997-06-27

    Applicant: Thomas Daniel ,  Anil Gupta

    Inventor： Thomas Daniel ,  Anil Gupta

    IPC: G06F9/46 ,  G06F9/45

    CPC classification number: G06F9/462

    Abstract: Microprocessor main programs and their interrupt handling routines are written in a high level programming language such as C. Each is compiled separately, and each is compiled invoking a compiler option which commands the compiler to not use a given set of registers in the compiled code. Post-processing is then performed on the compiled interrupt code to replace accesses to a first set of registers with accesses to the given set of registers. The result is that while both the main program and the interrupt handler were written in C, the compiled code for each employs different registers. This allows context switching from the main program to the interrupt handler and back again with almost none of the overhead traditionally associated with context switching register save and restore operations during exception handling.

    Abstract translation: 微处理器主程序及其中断处理例程以高级编程语言（如C）编写。每个编译单独编译，每个编译调用编译器选项，命令编译器在编译代码中不使用给定的一组寄存器。 然后对编译的中断代码进行后处理，以通过访问给定的寄存器组来替换对第一组寄存器的访问。 结果是当主程序和中断处理程序都用C编写时，每个编译代码使用不同的寄存器。 这允许从主程序到中断处理程序的上下文切换，并且在异常处理期间几乎没有传统上与上下文切换寄存器保存和恢复操作相关联的开销。

    ATM communication system interconnect/termination unit
    59.
    发明授权
    ATM communication system interconnect/termination unit 失效

    公开(公告)号：US5982749A

    公开(公告)日：1999-11-09

    申请号：US612112

    申请日：1996-03-07

    Applicant: Thomas Daniel ,  Dieter Nattkemper ,  Subir Varma

    Inventor： Thomas Daniel ,  Dieter Nattkemper ,  Subir Varma

    IPC: H04L12/56 ,  H04Q11/04 ,  G06F3/00

    CPC classification number: H04Q11/0478 ,  H04L2012/5616 ,  H04L2012/5652 ,  H04L2012/5679 ,  H04L2012/5681

    Abstract: An asynchronous transfer mode (ATM) digital electronic communication system includes an ATM communication system interconnection and termination unit (ATMCSI/TU). This ATMCSI/TU includes both a programmable microprocessor and several hardware-implemented coprocessors. The hardware-implemented coprocessors are under control of the microprocessor, and are dedicated to the performing of repetitive tasks. Thus, the microprocessor is freed to perform supervisory tasks in the ATM in addition to performing tasks associated with actual communication of digital data packages (i.e., CS-PDU's) in the ATM system. Thus, the APU is freed from doing repetitive data manipulation tasks, while these tasks are performed by one or more hardware-implemented coprocessors using memory mapped data structures and linked lists of data.

    Scheduler design for ATM switches, and its implementation in a distributed shared memory architecture
    60.
    发明授权
    Scheduler design for ATM switches, and its implementation in a distributed shared memory architecture 失效
    ATM交换机的调度器设计及其在分布式共享存储器架构中的实现

    公开(公告)号：US5959993A

    公开(公告)日：1999-09-28

    申请号：US714005

    申请日：1996-09-13

    Applicant: Subir Varma ,  Thomas Daniel

    Inventor： Subir Varma ,  Thomas Daniel

    IPC: H04L12/56 ,  H04J3/00

    CPC classification number: H04L49/30 ,  H04L49/103 ,  H04L49/107 ,  H04L49/20 ,  H04L49/3081 ,  H04L2012/5651 ,  H04L2012/5679 ,  H04L2012/5681

    Abstract: A cell scheduler for a distributed shared memory switch architecture including a controller for scheduling transmissions of cells from output queues of the switch structure pursuant to one of several different scheduling modes. The controller receives a mode selection input, segregates the output queues into groups, assigns priority rankings to the groups, and applies one of scheduling disciplines at each group of output queues as determined by the mode selection input and the priority rankings. The groups of output queues include a group of per-Virtual Channel (VC) queues and at least one group of First In-First Out (FIFO) queues. The scheduling disciplines include a Weighted Fair Queuing (WFQ) scheduling discipline applied by the controller at the group of per-VC queues and a Round Robin (RR) scheduling discipline applied by the controller at the at least one group of FIFO queues. The priority rankings comprising a highest priority ranking which is assigned to the group of per-VC queues.

    Abstract translation: 一种用于分布式共享存储器交换机架构的小区调度器，其包括用于根据若干不同调度模式之一调度来自交换机结构的输出队列的小区的传输的控制器。 控制器接收模式选择输入，将输出队列隔离成组，为组分配优先级排序，并根据模式选择输入和优先级排序确定每组输出队列中的调度规则之一。 输出队列组包括一组每个虚拟通道（VC）队列和至少一组先入先出（FIFO）队列。 调度规则包括控制器在每个VC队列组中应用的加权公平排队（WFQ）调度规则，以及控制器在至少一组FIFO队列中应用的循环（RR）调度规则。 优先级排名包括分配给每个VC队列组的最高优先级排名。

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