公开(公告)号：US10833067B1

公开(公告)日：2020-11-10

申请号：US16519135

申请日：2019-07-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Sipeng Gu ,  Jiehui Shu ,  Scott H. Beasor ,  Zhenyu Hu

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  H01L29/06

Abstract: A structure includes a first dielectric over a trench silicide (TS) contact and over a gate structure, and at least one cavity in the first dielectric. A metal resistor layer is on a bottom and sidewalls of the at least one cavity and extends over the first dielectric. A first contact is on the metal resistor layer over the first dielectric; and a second contact is on the metal resistor layer over the first dielectric. The metal resistor layer is over the TS contact and over the gate structure. Where a plurality of cavities are provided in the dielectric, a resistor structure formed by the metal resistor layer may have an undulating cross-section over the plurality of cavities and the dielectric.

公开(公告)号：US10714422B2

公开(公告)日：2020-07-14

申请号：US16161590

申请日：2018-10-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiaoqiang Zhang ,  Guoxiang Ning ,  Jiehui Shu

IPC: H01L23/525 ,  H01L21/768

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an anti-fuse with self-aligned via patterning and methods of manufacture. The anti-fuse includes: a lower wiring layer composed of a plurality of lower wiring structures; at least one via structure in direct contact and misaligned with a first wiring structure of the plurality of lower wiring structures and offset from a second wiring structure of the plurality of lower wiring structures; and an upper wiring layer composed of at least one upper wiring structure in direct contact with the at least one via structure.

公开(公告)号：US10714376B2

公开(公告)日：2020-07-14

申请号：US16016910

申请日：2018-06-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chih-Chiang Chang ,  Haifeng Sheng ,  Jiehui Shu ,  Haigou Huang ,  Pei Liu ,  Jinping Liu ,  Haiting Wang ,  Daniel J. Jaeger

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/768

Abstract: The present disclosure relates to methods for forming fill materials in trenches having different widths and related structures. A method may include: forming a first fill material in a first and second trench where the second trench has a greater width than the first trench; removing a portion of the first fill material from each trench and forming a second fill material over the first fill material; removing a portion of the first and second fill material within the second trench; and forming a third fill material in the second trench. The structure may include a first fill material in trenches having different widths wherein the upper surfaces of the first fill material in each trench are substantially co-planar. The structure may also include a second fill material on the first fill material in each trench, the second fill material having a substantially equal thickness in each trench.

公开(公告)号：US10692812B2

公开(公告)日：2020-06-23

申请号：US15980085

申请日：2018-05-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ravi Prakash Srivastava ,  Hui Zang ,  Jiehui Shu

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/308 ,  H01L21/02 ,  H01L21/033

Abstract: Methods of fabricating an interconnect structure. A hardmask is deposited over an interlayer dielectric layer, and a block mask is formed that covers an area on the hardmask. A sacrificial layer is formed over the block mask and the hardmask, and the sacrificial layer is patterned to form a mandrel that extends across the block mask.

公开(公告)号：US10593757B2

公开(公告)日：2020-03-17

申请号：US15961912

申请日：2018-04-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Ruilong Xie ,  Hui Zang ,  Haiting Wang

IPC: H01L29/08 ,  H01L29/78 ,  C30B29/40 ,  H01L29/66 ,  H01L21/02 ,  C30B25/04

Abstract: Methods form an integrated circuit structure that includes complementary transistors on a first layer. An isolation structure is between the complementary transistors. Each of the complementary transistors includes source/drain regions and a gate conductor between the source/drain regions, and insulating spacers are between the gate conductor and the source/drain regions in each of the complementary transistors. With these methods and structures, an etch stop layer is formed only on the source/drain regions.

公开(公告)号：US10586860B2

公开(公告)日：2020-03-10

申请号：US15970217

申请日：2018-05-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Laertis Economikos ,  Xusheng Wu ,  John Zhang ,  Haigou Huang ,  Hui Zhan ,  Tao Han ,  Haiting Wang ,  Jinping Liu ,  Hui Zang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8238 ,  H01L21/3065

Abstract: In conjunction with a replacement metal gate (RMG) process for forming a fin field effect transistor (FinFET), gate isolation methods and associated structures leverage the formation of distinct narrow and wide gate cut regions in a sacrificial gate. The formation of a narrow gate cut between closely-spaced fins can decrease the extent of etch damage to interlayer dielectric layers located adjacent to the narrow gate cut by delaying the deposition of such dielectric layers until after formation of the narrow gate cut opening. The methods and resulting structures also decrease the propensity for short circuits between later-formed, adjacent gates.

公开(公告)号：US10573753B1

公开(公告)日：2020-02-25

申请号：US16126775

申请日：2018-09-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Laertis Economikos ,  Jiehui Shu ,  Ruilong Xie

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L23/532 ,  H01L21/768 ,  H01L21/762 ,  H01L29/06 ,  H01L21/02 ,  H01L29/417

Abstract: A device including oxide spacer in a contact over active gates (COAG) and method of production thereof. Embodiments include first gate structures over a fin of a substrate and second gate structures, each over an outer portion of the fin and a shallow trench isolation (STI) layer adjacent to the fin; a first raised source/drain (RSD) in a portion of the fin between the first gate structures and a second RSD in the portion of the fin between the first and second gate structures; a metal liner over the first and second RSD and on sidewall portions of the first and second gate structures; a metal layer over the metal liner; and an interlayer dielectric (ILD) over the metal liner and portions of the first and second gate structures.

公开(公告)号：US10510613B2

公开(公告)日：2019-12-17

申请号：US15878081

申请日：2018-01-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Xusheng Wu ,  Haigou Huang ,  John H. Zhang ,  Pei Liu ,  Laertis Economikos

IPC: H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L23/535 ,  H01L21/28

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a contact over an active gate structure and methods of manufacture. The structure includes: an active gate structure composed of conductive material located between sidewall material; an upper sidewall material above the sidewall material, the upper sidewall material being different material than the sidewall material; and a contact structure in electrical contact with the conductive material of the active gate structure. The contact structure is located between the sidewall material and between the upper sidewall material.

公开(公告)号：US20190355658A1

公开(公告)日：2019-11-21

申请号：US15980085

申请日：2018-05-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ravi Prakash Srivastava ,  Hui Zang ,  Jiehui Shu

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/308 ,  H01L21/02 ,  H01L21/033

Abstract: Methods of fabricating an interconnect structure. A hardmask is deposited over an interlayer dielectric layer, and a block mask is formed that covers an area on the hardmask. A sacrificial layer is formed over the block mask and the hardmask, and the sacrificial layer is patterned to form a mandrel that extends across the block mask.

公开(公告)号：US10475791B1

公开(公告)日：2019-11-12

申请号：US15994231

申请日：2018-05-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Garo Jacques Derderian ,  Laertis Economikos ,  Chun Yu Wong ,  Jiehui Shu ,  Shesh Mani Pandey

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/8234

Abstract: First and second fin-type field effect transistors (finFETs) are formed laterally adjacent one another extending from a top surface of an isolation layer. The first finFET has a first fin structure and the second finFET has a second fin structure. An insulator layer is on the first fin structure and the second fin structure. A gate conductor intersects the first fin structure and the second fin structure, and at least the insulator layer separates the gate conductor from the first fin structure and the second fin structure. Source and drain structures are on the first fin structure and the second fin structure laterally adjacent the gate conductor. The first fin structure has sidewalls that include a step and the second fin structure has sidewalls that do not include the step. The step is approximately parallel to the surface of the isolation layer.