公开(公告)号：US20190326286A1

公开(公告)日：2019-10-24

申请号：US15958426

申请日：2018-04-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Steven Soss ,  Steven Bentley ,  Daniel Chanemougame ,  Julien Frougier ,  Bipul Paul ,  Lars Liebmann

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/66 ,  H01L29/423

Abstract: A semiconductor device at least one first transistor of a first type disposed above a substrate and comprising a channel wider in one cross-section than tall, wherein the first type is a PFET transistor or an NFET transistor; and at least one second transistor of a second type disposed above the at least one first transistor and comprising a channel taller in the one cross-section than wide, wherein the second type is a PFET transistor or an NFET transistor, and the second type is different from the first type. Methods and systems for forming the semiconductor structure.

公开(公告)号：US20190206878A1

公开(公告)日：2019-07-04

申请号：US15861161

申请日：2018-01-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Daniel Chanemougame ,  Emilie Bourjot

IPC: H01L27/11 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/1104 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/41741 ,  H01L29/7827

Abstract: One illustrative IC product disclosed herein includes a first merged doped source/drain region that includes first and second doped regions and an isolation structure positioned adjacent the first doped region. In this example, the product also includes a contact structure positioned adjacent the isolation structure, wherein the contact structure includes a first portion positioned below an upper surface of the first merged doped source/drain region and a second portion positioned above the upper surface, wherein the first portion physically contacts both the first and second doped regions. The product also includes a layer of insulating material positioned on and in physical contact with a portion of an upper surface of the first portion of the contact structure.

公开(公告)号：US10304832B1

公开(公告)日：2019-05-28

申请号：US15814440

申请日：2017-11-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel Chanemougame ,  Lars Liebmann ,  Ruilong Xie

IPC: H01L23/58 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/417 ,  H01L29/06

Abstract: Disclosed are integrated circuit (IC) structure embodiments that incorporate stacked pair(s) of field effect transistors (FETs) (e.g., gate-all-around FETs), including a lower FET and an upper FET on the lower FET, and various metal components that enable power and/or signal connections to the source/drain regions of those FETs. The metal components can include first buried wire(s) within an isolation region in a level below the stacked pair and a first embedded contact that electrically connects a source/drain region of the lower FET to a first buried wire. Optionally, the metal components can also include second buried wire(s) in dielectric material at the same level as the upper FET and a second embedded contact that electrically connects a source/drain region of the upper FET to a second buried wire. Also disclosed are embodiments of a method of forming such IC structure embodiments.

公开(公告)号：US20190148494A1

公开(公告)日：2019-05-16

申请号：US15814724

申请日：2017-11-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Lars Liebmann ,  Daniel Chanemougame ,  Chanro Park ,  John H. Zhang ,  Steven Bentley ,  Hui Zang

IPC: H01L29/10 ,  H01L29/78 ,  H01L27/24 ,  H01L21/8234

Abstract: A first vertical field effect transistor (VFET) and a second VFET are formed on a substrate. The VFETs are parallel and adjacent to one another, and each comprises: a fin-shaped semiconductor; a lower source/drain (S/D) element; an upper S/D element; and a gate conductor. A portion of a gate conductor of the second VFET that is positioned over a lower S/D element of the second VFET is removed to leave a trench. An isolation spacer is formed to contact the gate conductor of the second VFET in a first portion of the trench. A lower S/D contact of the second VFET is formed on the lower S/D element of the second VFET in a second portion of the trench, a lower S/D contact of the first VFET is formed to a lower S/D element of the first VFET, and contacts are formed.

公开(公告)号：US20190148376A1

公开(公告)日：2019-05-16

申请号：US15814440

申请日：2017-11-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel Chanemougame ,  Lars Liebmann ,  Ruilong Xie

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/06 ,  H01L29/417

Abstract: Disclosed are integrated circuit (IC) structure embodiments that incorporate stacked pair(s) of field effect transistors (FETs) (e.g., gate-all-around FETs), including a lower FET and an upper FET on the lower FET, and various metal components that enable power and/or signal connections to the source/drain regions of those FETs. The metal components can include first buried wire(s) within an isolation region in a level below the stacked pair and a first embedded contact that electrically connects a source/drain region of the lower FET to a first buried wire. Optionally, the metal components can also include second buried wire(s) in dielectric material at the same level as the upper FET and a second embedded contact that electrically connects a source/drain region of the upper FET to a second buried wire. Also disclosed are embodiments of a method of forming such IC structure embodiments.

公开(公告)号：US10269812B1

公开(公告)日：2019-04-23

申请号：US15814724

申请日：2017-11-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Lars Liebmann ,  Daniel Chanemougame ,  Chanro Park ,  John H. Zhang ,  Steven Bentley ,  Hui Zang

IPC: H01L27/112 ,  H01L29/10 ,  H01L21/8234 ,  H01L27/24 ,  H01L29/78 ,  H01L29/808 ,  H01L45/00 ,  H01L29/66 ,  H01L29/06 ,  H01L23/522 ,  H01L21/02

Abstract: A first vertical field effect transistor (VFET) and a second VFET are formed on a substrate. The VFETs are parallel and adjacent to one another, and each comprises: a fin-shaped semiconductor; a lower source/drain (S/D) element; an upper S/D element; and a gate conductor. A portion of a gate conductor of the second VFET that is positioned over a lower S/D element of the second VFET is removed to leave a trench. An isolation spacer is formed to contact the gate conductor of the second VFET in a first portion of the trench. A lower S/D contact of the second VFET is formed on the lower S/D element of the second VFET in a second portion of the trench, a lower S/D contact of the first VFET is formed to a lower S/D element of the first VFET, and contacts are formed.

公开(公告)号：US20190109045A1

公开(公告)日：2019-04-11

申请号：US15728632

申请日：2017-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Lars W. Liebmann ,  Daniel Chanemougame ,  Chanro Park

IPC: H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L23/528 ,  H01L23/522

Abstract: One illustrative method disclosed herein may include forming a contact etching structure in a layer of insulating material positioned above first and second lower conductive structures, wherein at least a portion of the contact etching structure is positioned laterally between the first and second lower conductive structures, forming a first conductive line and a first conductive contact adjacent a first side of the contact etching structure and forming a second conductive line and a second conductive contact adjacent a second side of the contact etching structure, wherein a spacing between the first and second conductive lines is approximately equal to a dimension of the contact etching structure.

公开(公告)号：US10236215B1

公开(公告)日：2019-03-19

申请号：US15791711

申请日：2017-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Daniel Chanemougame ,  Bipul C. Paul ,  Lars W. Liebmann ,  Heimanu Niebojewski ,  Xuelian Zhu ,  Lei Sun ,  Hui Zang

IPC: H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L27/088 ,  H01L23/528

Abstract: One illustrative method disclosed includes, among other things, forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure, wherein an upper surface of each of these contact structures are positioned at a first level. In one example, this method also includes forming a masking layer that covers the initial CB gate contact structure and exposes the initial GSD contact structure and, with the masking layer in position, performing a recess etching process on the initial GSD contact structure so as to form a recessed GSD contact structure, wherein a recessed upper surface of the recessed GSD contact structure is positioned at a second level that is below the first level.

公开(公告)号：US10192819B1

公开(公告)日：2019-01-29

申请号：US15814435

申请日：2017-11-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel Chanemougame ,  Lars Liebmann ,  Ruilong Xie

IPC: H01L29/00 ,  H01L23/50 ,  H01L25/07 ,  H01L29/417 ,  H01L21/8234

Abstract: Disclosed are integrated circuit (IC) structure embodiments that incorporate a stacked pair of field effect transistors (FETs) (e.g., gate-all-around FETs) and metal components that enable power and/or signal connections to source/drain regions of those FETs. Specifically, the IC includes a first FET and a second FET stacked on and sharing a gate with the first FET. The metal components include an embedded contact in a source/drain region of the first FET and connected to a wire (e.g., a power or signal wire). The wire can be a front end of the line (FEOL) wire positioned laterally adjacent to the source/drain region and the embedded contact can extend laterally from the source/drain region to the FEOL wire. Alternatively, the wire can be a back end of the line (BEOL) wire and an insulated contact can extend vertically from the embedded contact through the second FET to the BEOL wire.

公开(公告)号：US20200083352A1

公开(公告)日：2020-03-12

申请号：US16123160

申请日：2018-09-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel Chanemougame ,  Julien Frougier ,  Ruilong Xie

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423

Abstract: Disclosed are structures including a gate-all-around field effect transistor (GAAFET) with air-gap inner spacers. The GAAFET includes a stack of nanoshapes that extend laterally between source/drain regions, a gate that wraps around a center portion of each nanoshape, and a gate sidewall spacer on external sidewalls of the gate. The GAAFET also includes air-gap inner spacers between the gate and the source/drain regions. Each air-gap inner spacer includes: two vertical sections within the gate sidewall spacer on opposing sides of the stack and adjacent to a source/drain region; and horizontal sections below the nanoshapes and extending laterally between the vertical sections. Also discloses are methods of forming the structures and the method include forming preliminary inner spacers in inner spacer cavities prior to source/drain region formation. After source/drain regions are formed, the preliminary inner spacers are removed and the cavities are sealed off, thereby forming the air-gap inner spacers.