公开(公告)号：US20110096611A1

公开(公告)日：2011-04-28

申请号：US12929123

申请日：2011-01-03

Applicant: Kwang Jin Lee ,  Joon Min Park ,  Hye-Jin Kim

Inventor： Kwang Jin Lee ,  Joon Min Park ,  Hye-Jin Kim

IPC: G11C7/00

CPC classification number: G11C13/0069 ,  G11C7/22 ,  G11C8/12 ,  G11C13/0004 ,  G11C2013/0076 ,  G11C2207/2209

Abstract: A semiconductor device according to example embodiments may be configured so that, when a read command for performing a read operation is input while a write operation is performed, and when a memory bank accessed by a write address during the write operation is the same as a memory bank accessed by a read address during the read operation, the semiconductor device may suspend the write operation automatically or in response to an internal signal until the read operation is finished and performs the write operation after the read operation is finished.

公开(公告)号：US20110095424A1

公开(公告)日：2011-04-28

申请号：US12855322

申请日：2010-08-12

Applicant: In-Sang Song ,  Hye-Jin Kim ,  Kyung-Man Kim

Inventor： In-Sang Song ,  Hye-Jin Kim ,  Kyung-Man Kim

IPC: H01L23/498

CPC classification number: H01L25/105 ,  H01L21/568 ,  H01L23/481 ,  H01L23/49833 ,  H01L25/0657 ,  H01L2224/02377 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/13024 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/9205 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311

Abstract: The semiconductor package structure includes first and second packages. The first package has at least one first semiconductor chip disposed on a first printed circuit board, and at least one first pad disposed on the at least one first semiconductor chip. The second package has at least one second pad disposed on the first package, and at least one second semiconductor chip disposed on the at least one second pad. The at least one first semiconductor chip is electrically connected to the first printed circuit board. The at least one second pad is electrically connected to the at least one second semiconductor chip. The at least one second pad faces the at least one first pad.

Abstract translation: 半导体封装结构包括第一和第二封装。 第一封装具有设置在第一印刷电路板上的至少一个第一半导体芯片和设置在至少一个第一半导体芯片上的至少一个第一焊盘。 所述第二封装具有设置在所述第一封装上的至少一个第二焊盘以及设置在所述至少一个第二焊盘上的至少一个第二半导体芯片。 所述至少一个第一半导体芯片电连接到所述第一印刷电路板。 所述至少一个第二焊盘电连接到所述至少一个第二半导体芯片。 所述至少一个第二垫面对所述至少一个第一垫。

公开(公告)号：US07634113B2

公开(公告)日：2009-12-15

申请号：US11291607

申请日：2005-11-30

Applicant: Do-Hyung Kim ,  Jae-Yeon Lee ,  Su-Young Chi ,  Ho-Sub Yoon ,  Kye-Kyung Kim ,  Soo-Hyun Cho ,  Hye-Jin Kim ,  Young-Jo Cho

Inventor： Do-Hyung Kim ,  Jae-Yeon Lee ,  Su-Young Chi ,  Ho-Sub Yoon ,  Kye-Kyung Kim ,  Soo-Hyun Cho ,  Hye-Jin Kim ,  Young-Jo Cho

IPC: G06K9/00 ,  G06K5/00 ,  G05B19/00 ,  G10L21/00

CPC classification number: G06K9/00362

Abstract: A user recognizing system and method is provided. According to the user recognizing system and method, user ID and predetermined user feature information are stored, first and second user feature information are extracted from the user image data transmitted from the image input unit, and first and second probabilities that the extracted first and second user feature information determine the predetermined user are respectively generated based on the information stored at the user information database, the first user feature information being absolutely unique biometric information and the second user feature information being unique semibiometric information under a predetermined condition, and ID of the input image is finally determined by combining the first probability and the second probability. According to the user recognizing system and method, a user identity can be authenticated even when the user freely moves.

Abstract translation: 提供了一种用户识别系统和方法。 根据用户识别系统和方法，存储用户ID和预定用户特征信息，从从图像输入单元发送的用户图像数据中提取第一和第二用户特征信息，以及提取的第一和第二概率的第一和第二概率 基于存储在用户信息数据库中的信息分别生成预定用户的用户特征信息，第一用户特征信息是绝对唯一的生物体信息，第二用户特征信息是预定条件下的唯一半身测量信息，以及ID 最终通过组合第一概率和第二概率来确定输入图像。 根据用户识别系统和方法，即使用户自由移动，也可以认证用户身份。

公开(公告)号：US20090303807A1

公开(公告)日：2009-12-10

申请号：US12453872

申请日：2009-05-26

Applicant: Kwang Jin Lee ,  Joon Min Park ,  Hye-Jin Kim

Inventor： Kwang Jin Lee ,  Joon Min Park ,  Hye-Jin Kim

IPC: G11C7/00 ,  G11C11/00

CPC classification number: G11C13/0069 ,  G11C7/22 ,  G11C8/12 ,  G11C13/0004 ,  G11C2013/0076 ,  G11C2207/2209

Abstract: A semiconductor device according to example embodiments may be configured so that, when a read command for performing a read operation is input while a write operation is performed, and when a memory bank accessed by a write address during the write operation is the same as a memory bank accessed by a read address during the read operation, the semiconductor device may suspend the write operation automatically or in response to an internal signal until the read operation is finished and performs the write operation after the read operation is finished.

Abstract translation: 根据示例实施例的半导体器件可以被配置为使得当执行写入操作时输入用于执行读取操作的读取命令，并且当在写入操作期间由写入地址访问的存储体组与 存储体在读取操作期间由读取地址访问，半导体器件可以自动暂停写入操作或响应于内部信号直到读取操作完成，并且在读取操作完成之后执行写入操作。

公开(公告)号：US20090154221A1

公开(公告)日：2009-06-18

申请号：US12314513

申请日：2008-12-11

Applicant: Hye-Jin Kim ,  Kwang-Jin Lee ,  Du-Eung Kim ,  Hung-Jun An

Inventor： Hye-Jin Kim ,  Kwang-Jin Lee ,  Du-Eung Kim ,  Hung-Jun An

IPC: G11C11/00 ,  G11C7/00 ,  G11C5/14

CPC classification number: G11C7/1078 ,  G11C5/14 ,  G11C7/1096 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/72

Abstract: A non-volatile memory device using a variable resistive element is provided. The non-volatile memory device includes a memory cell array having a plurality of non-volatile memory cells, a first voltage generator generating a first voltage, a voltage pad receiving an external voltage that has a level higher than the first voltage, a sense amplifier supplied with the first voltage and reading data from the non-volatile memory cells selected from the memory cell array, and a write driver supplied with the external voltage and writing data to the non-volatile memory cells selected from the memory cell array.

Abstract translation: 提供了使用可变电阻元件的非易失性存储器件。 非易失性存储器件包括具有多个非易失性存储器单元的存储单元阵列，产生第一电压的第一电压发生器，接收高于第一电压的电平的外部电压的电压焊盘，读出放大器 提供第一电压并从存储单元阵列中选择的非易失性存储单元读取数据，以及提供有外部电压的写入驱动器，并将数据写入从存储单元阵列中选择的非易失性存储单元。

公开(公告)号：US20060181915A1

公开(公告)日：2006-08-17

申请号：US11319266

申请日：2005-12-29

Applicant: Hyung-Rok Oh ,  Woo-Yeong Cho ,  Hye-Jin Kim

Inventor： Hyung-Rok Oh ,  Woo-Yeong Cho ,  Hye-Jin Kim

IPC: G11C11/00

CPC classification number: G11C13/004 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2213/79

Abstract: A semiconductor memory device includes a plurality of phase change memory cells connected to the same bitline and different respective word lines. A read operation is performed on one of the memory cells by selecting the bitline and a corresponding wordline. While the read operation is performed, leakage current produced by non-selected memory cells is detected by a leakage detecting circuit and compensated by a leakage current supply circuit.

Abstract translation: 半导体存储器件包括连接到同一位线和不同相应字线的多个相变存储器单元。 通过选择位线和相应的字线，对存储器单元之一执行读取操作。 在执行读取操作的同时，由漏电检测电路检测由未选择的存储单元产生的漏电流，并由泄漏电流供给电路进行补偿。

公开(公告)号：US20060140481A1

公开(公告)日：2006-06-29

申请号：US11287936

申请日：2005-11-28

Applicant: Kye-Kyung Kim ,  Soo-Hyun Cho ,  Hye-Jin Kim ,  Jae-Yeon Lee

Inventor： Kye-Kyung Kim ,  Soo-Hyun Cho ,  Hye-Jin Kim ,  Jae-Yeon Lee

IPC: G06K9/46 ,  H04N5/228

CPC classification number: H04N5/232 ,  G06K9/00362 ,  G06T7/246

Abstract: A target detecting system and method for detecting a target from an input image is provided. According to the target detecting system and method, when a target is detected from an input image and there are moving areas in the input image, camera movement parameters are obtained, image frames are transformed, and movement candidate areas are extracted from the image frame and the previous input image frame. In addition, image feature information is extracted from the input image, and based on the movement candidate areas and the image feature information a shape of the target is extracted. Therefore, the target can be exactly and rapidly extracted and tracked.

Abstract translation: 提供了一种从输入图像中检测目标的目标检测系统和方法。 根据目标检测系统和方法，当从输入图像检测到目标并且在输入图像中存在移动区域时，获得相机移动参数，变换图像帧，并且从图像帧中提取移动候选区域，并且 以前的输入图像帧。 此外，从输入图像中提取图像特征信息，并且基于移动候选区域和图像特征信息，提取目标的形状。 因此，可以准确，快速地提取和跟踪目标。

公开(公告)号：US20060092690A1

公开(公告)日：2006-05-04

申请号：US11260602

申请日：2005-10-27

Applicant: Hye-Jin Kim ,  Woo-Yeong Cho ,  Hyung-Rok Oh

Inventor： Hye-Jin Kim ,  Woo-Yeong Cho ,  Hyung-Rok Oh

IPC: G11C11/00

CPC classification number: H03L7/0812 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/16 ,  G11C11/5607 ,  G11C2211/5615 ,  H01L27/228 ,  H03L7/0891

Abstract: A magnetic random access memory (RAM) with a multi-bit cell array structure includes an access transistor formed on a substrate, first through third resistance-variable elements, and first through third current supplying lines. The first through third resistance-variable elements are disposed between a bit line and the access transistor, and electrically connected to each other. The first through third current supplying lines are stacked alternately with the first through third resistance-variable elements. The first through third resistance-variable elements have equal resistances.

Abstract translation: 具有多比特单元阵列结构的磁随机存取存储器（RAM）包括形成在基片上的存取晶体管，第一至第三电阻可变元件以及第一至第三电流线。 第一至第三电阻可变元件设置在位线和存取晶体管之间，并且彼此电连接。 第一至第三电流供应线与第一至第三电阻可变元件交替堆叠。 第一至第三电阻可变元件具有相等的电阻。