公开(公告)号：US20150311163A1

公开(公告)日：2015-10-29

申请号：US14791026

申请日：2015-07-02

Applicant: Infineon Technologies AG

Inventor： Erwin Vogl ,  Markus Zundel

IPC: H01L23/00 ,  H01L29/04 ,  H01L23/48 ,  H01L29/06

CPC classification number: H01L23/562 ,  H01L23/481 ,  H01L23/4824 ,  H01L29/04 ,  H01L29/0692 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

Abstract: An anchoring structure for a metal structure of a semiconductor device includes an anchoring recess structure having at least one overhanging side wall, the metal structure being at least partly arranged within the anchoring recess structure.

Abstract translation: 用于半导体器件的金属结构的锚定结构包括具有至少一个悬垂侧壁的锚固凹槽结构，金属结构至少部分地布置在锚定凹槽结构内。

公开(公告)号：US09142401B2

公开(公告)日：2015-09-22

申请号：US14305359

申请日：2014-06-16

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Alexander Susiti ,  Markus Zundel ,  Reinhard Ploss

IPC: H01L27/108 ,  H01L21/02 ,  H01L23/29 ,  H01L23/31 ,  H01L29/10 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L29/739 ,  H01L21/3115 ,  H01L29/06 ,  H01L29/423 ,  H01L29/40

CPC classification number: H01L29/7813 ,  H01L21/02123 ,  H01L21/02129 ,  H01L21/02321 ,  H01L21/26506 ,  H01L21/283 ,  H01L21/3115 ,  H01L21/31155 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/06 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4916 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device includes forming a continuous silicate glass structure over a first surface of a semiconductor body, including a first part of the continuous glass structure over an active area of the semiconductor body and a second part of the continuous glass structure over an area of the semiconductor body outside of the active area. A first composition of dopants included in the first part of continuous glass structure differs from a second composition of dopants of the second part of the continuous glass structure.

Abstract translation: 一种制造半导体器件的方法包括在半导体本体的第一表面上形成连续的硅酸盐玻璃结构，该第一表面包括半导体本体的有源区域上的连续玻璃结构的第一部分和连续玻璃结构的第二部分， 半导体主体的有效区域外的区域。 连续玻璃结构的第一部分中包括的掺杂剂的第一组合物不同于连续玻璃结构的第二部分的第二种掺杂剂组合物。

公开(公告)号：US09123559B2

公开(公告)日：2015-09-01

申请号：US13906425

申请日：2013-05-31

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Markus Zundel

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L21/762 ,  H01L29/40

CPC classification number: H01L29/0696 ,  H01L21/28008 ,  H01L21/76224 ,  H01L21/76229 ,  H01L29/407 ,  H01L29/42356 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66348 ,  H01L29/66704 ,  H01L29/7813

Abstract: Methods for producing a semiconductor component that includes a transistor having a cell structure with a number of transistor cells monolithically integrated in a semiconductor body and electrically connected in parallel. In an example method, first trenches extending from the top side into the semiconductor body are produced, as are second trenches that each extend from the top side deeper into the semiconductor body than each of the first trenches. A first dielectric abutting on a first portion of the semiconductor body is produced at a surface of each of the first trenches. Also produced is a second dielectric at a surface of each of the second trenches. In each of the first trenches, a gate electrode is produced, after which a second portion of the semiconductor body is electrically insulated from the first portion of the semiconductor body by removing a bottom layer of the semiconductor body.

Abstract translation: 一种用于制造半导体元件的方法，该半导体元件包括晶体管，晶体管具有单个集成在半导体本体中并并联连接的多个晶体管单元的单元结构。 在示例性方法中，产生从顶侧延伸到半导体本体的第一沟槽，以及从第一沟槽中分别从第一沟槽的顶侧延伸到比第一沟槽中的每一个更深的半导体本体。 在每个第一沟槽的表面上产生邻接在半导体本体的第一部分上的第一电介质。 还产生在每个第二沟槽的表面处的第二电介质。 在每个第一沟槽中，制造栅电极，之后半导体本体的第二部分通过去除半导体本体的底层而与半导体本体的第一部分电绝缘。

公开(公告)号：US20150221523A1

公开(公告)日：2015-08-06

申请号：US14598288

申请日：2015-01-16

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Andre Schmenn ,  Damian Sojka ,  Isabella Goetz ,  Gudrun Stranzl ,  Sebastian Werner ,  Thomas Fischer ,  Carsten Ahrens ,  Edward Fuergut

IPC: H01L21/3213 ,  H01L21/283 ,  H01L27/02 ,  H01L21/306 ,  H01L23/498 ,  H01L21/56 ,  H01L21/304

CPC classification number: H01L21/561 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/49838 ,  H01L27/0248 ,  H01L27/0255 ,  H01L29/861 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/00

Abstract: An arrangement is provided. The arrangement may include: a substrate having a front side and a back side, a die region within the substrate, a multi-purpose layer defining a back side of the die region, and an etch stop layer disposed over the multi-purpose layer between the multi-purpose layer and the back side of the substrate. The multi-purpose layer may be formed of an ohmic material, and the etch stop layer may be of a first conductivity type of a first doping concentration.

Abstract translation: 提供了一种安排。 该布置可以包括：具有前侧和后侧的基板，基板内的管芯区域，限定管芯区域的背面的多用途层以及设置在多用途层之间的蚀刻停止层， 多用途层和背面。 多用途层可以由欧姆材料形成，并且蚀刻停止层可以是第一掺杂浓度的第一导电类型。

公开(公告)号：US09099419B2

公开(公告)日：2015-08-04

申请号：US13647480

申请日：2012-10-09

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Franz Hirler ,  Peter Nelle

IPC: G01R31/26 ,  H01L21/66 ,  G01R31/28

CPC classification number: G01R31/2601 ,  G01R31/2884 ,  H01L22/32 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A test method in accordance with one or more embodiments may include: providing a semiconductor device to be tested, the semiconductor device including at least one device cell, the at least one device cell having at least one trench, at least one first terminal electrode region and at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one additional electrode may be controlled separately from electrical potentials of the at least one first terminal electrode region, the at least one second terminal electrode region and the at least one gate electrode; and applying at least one electrical test potential to at least the at least one additional electrode to detect defects in the at least one device cell.

Abstract translation: 根据一个或多个实施例的测试方法可以包括：提供待测试的半导体器件，所述半导体器件包括至少一个器件单元，所述至少一个器件单元具有至少一个沟槽，至少一个第一端子电极区域 以及至少一个第二端子电极区域，至少一个栅极电极和至少部分地设置在所述至少一个沟槽中的至少一个附加电极，其中所述至少一个附加电极的电势可以与电势分开地控制 所述至少一个第一端子电极区域，所述至少一个第二端子电极区域和所述至少一个栅极电极; 以及向至少一个附加电极施加至少一个电测试电位以检测所述至少一个器件单元中的缺陷。

公开(公告)号：US20150162192A1

公开(公告)日：2015-06-11

申请号：US14102107

申请日：2013-12-10

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Markus Zundel ,  Anton Mauder ,  Andreas Meiser ,  Franz Hirler ,  Hans Weber

IPC: H01L21/02 ,  H01L21/265

CPC classification number: H01L21/02258 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/02299 ,  H01L21/02345 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/32105 ,  H01L29/66325 ,  H01L29/66477

Abstract: A method for forming a semiconductor device includes carrying out an anodic oxidation of a surface region of a semiconductor substrate to form an oxide layer at a surface of the semiconductor substrate by generating an attracting electrical field between the semiconductor substrate and an external electrode within an electrolyte to attract oxidizing ions of the electrolyte, causing an oxidation of the surface region of the semiconductor substrate. Further, the method includes reducing the number of remaining oxidizing ions within the oxide layer, while the semiconductor substrate is within an electrolyte.

Abstract translation: 一种形成半导体器件的方法包括：通过在半导体衬底和半导体衬底内的外部电极之间产生吸引电场，在半导体衬底的表面上进行半导体衬底的表面区域的阳极氧化以形成氧化物层 以吸引电解质的氧化离子，引起半导体衬底的表面区域的氧化。 此外，该方法包括减少氧化物层内剩余氧化离子的数量，同时半导体衬底在电解质内。

公开(公告)号：US09054150B2

公开(公告)日：2015-06-09

申请号：US14032437

申请日：2013-09-20

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Gabriela Brase ,  Peter Nelle ,  Guenther Schindler

IPC: H01L29/739 ,  H01L29/78 ,  H01L23/31 ,  H01L29/40 ,  H01L29/06

CPC classification number: H01L29/7393 ,  H01L23/3178 ,  H01L23/3192 ,  H01L29/0657 ,  H01L29/407 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to a semiconductor component comprising a semiconductor body, an insulation on the semiconductor body and a cell array arranged at least partly within the semiconductor body. The cell array has at least one p-n junction and at least one contact connection. The insulation is bounded in lateral direction of the semiconductor body by a circumferential diffusion barrier.

Abstract translation: 本发明涉及半导体元件，其包括半导体本体，半导体主体上的绝缘体和至少部分地布置在半导体本体内的电池阵列。 电池阵列具有至少一个p-n结和至少一个接触连接。 绝缘体通过周向扩散阻挡层在半导体主体的横向方向上界定。

公开(公告)号：US09006798B2

公开(公告)日：2015-04-14

申请号：US13886305

申请日：2013-05-03

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Manfred Schneegans

IPC: H01L27/148 ,  H01L29/04 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/045 ,  H01L21/823487 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

Abstract: A semiconductor device includes a trench transistor cell array in a silicon semiconductor body with a first main surface and a second main surface opposite to the first main surface. A main lateral face of the semiconductor body between the first main surface and the second main surface has a first length along a first lateral direction parallel to the first and second main surfaces. The first length is equal or greater than lengths of other lateral faces of the semiconductor body. The trench transistor cell array includes predominantly linear gate trench portions. At least 50% of the linear gate trench portions extend along a second lateral direction or perpendicular to the second lateral direction. An angle between the first and second lateral directions is in a range of 45°±15°.

Abstract translation: 半导体器件包括硅半导体本体中的沟槽晶体管单元阵列，其具有与第一主表面相对的第一主表面和第二主表面。 第一主表面和第二主表面之间的半导体本体的主侧面具有沿着平行于第一和第二主表面的第一横向方向的第一长度。 第一长度等于或大于半导体本体的其它侧面的长度。 沟槽晶体管单元阵列主要包括线性栅极沟槽部分。 至少50％的线性栅极沟槽部分沿着第二横向方向或垂直于第二横向方向延伸。 第一和第二横向之间的角度在45°±15°的范围内。

公开(公告)号：US20150064879A1

公开(公告)日：2015-03-05

申请号：US14013822

申请日：2013-08-29

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt ,  Gudrun Stranzl ,  Markus Zundel ,  Hubert Maier

IPC: H01L21/78 ,  B28D5/00 ,  H01J37/32

CPC classification number: H01J37/32009 ,  B28D5/00 ,  H01J2237/334 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834

Abstract: Various methods and apparatuses are provided relating to separation of a substrate into a plurality of parts. For example, first a partial separation is performed and then the partially separated substrate is completely separated into a plurality of parts.

Abstract translation: 提供了关于将基板分离成多个部件的各种方法和装置。 例如，首先进行部分分离，然后将部分分离的基板完全分离成多个部分。

公开(公告)号：US20150061003A1

公开(公告)日：2015-03-05

申请号：US14013804

申请日：2013-08-29

Applicant: Infineon Technologies AG

Inventor： Markus Zundel

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L23/3121 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/7397 ,  H01L29/7813 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40247 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49175 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/12036 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A power semiconductor package includes a housing, a semiconductor chip embedded in the housing, and at least four terminals partially embedded in the housing and partially exposed to the outside of the housing. The semiconductor chip includes a first doping region in ohmic contact with a first metal layer, a second doping region in ohmic contact with a second metal layer, and a plurality of first trenches that includes gate electrodes and first field electrodes electrically insulated from the gate electrodes. A first terminal of the four terminals is electrically connected to the first metal layer, a second terminal of the four terminals is electrically connected to the second metal layer, a third terminal of the four terminals is electrically connected to the gate electrodes of the first trenches, and a fourth terminal of the four terminals is electrically connected to the first field electrodes of the first trenches.

Abstract translation: 功率半导体封装包括壳体，嵌入壳体中的半导体芯片以及部分地嵌入壳体中并且部分地暴露于壳体外部的至少四个端子。 半导体芯片包括与第一金属层欧姆接触的第一掺杂区域，与第二金属层欧姆接触的第二掺杂区域和包括栅电极和与栅电极电绝缘的第一场电极的多个第一沟槽 。 四个端子的第一端子电连接到第一金属层，四个端子的第二端子电连接到第二金属层，四个端子的第三端子电连接到第一沟槽的栅极电极 并且四个端子的第四端子电连接到第一沟槽的第一场电极。