公开(公告)号：US12271735B2

公开(公告)日：2025-04-08

申请号：US18419059

申请日：2024-01-22

Applicant: Intel Corporation

Inventor： Ahmad Yasin ,  Raanan Sade ,  Liron Zur ,  Igor Yanover ,  Joseph Nuzman

IPC: G06F9/30 ,  G06F9/54 ,  G06F11/30 ,  G06F11/34

Abstract: Systems, methods, and apparatuses relating to circuitry to precisely monitor memory store accesses are described. In one embodiment, a system includes a memory, a hardware processor core comprising a decoder to decode an instruction into a decoded instruction, an execution circuit to execute the decoded instruction to produce a resultant, a store buffer, and a retirement circuit to retire the instruction when a store request for the resultant from the execution circuit is queued into the store buffer for storage into the memory, and a performance monitoring circuit to mark the retired instruction for monitoring of post-retirement performance information between being queued in the store buffer and being stored in the memory, enable a store fence after the retired instruction to be inserted that causes previous store requests to complete within the memory, and on detection of completion of the store request for the instruction in the memory, store the post-retirement performance information in storage of the performance monitoring circuit.

公开(公告)号：US20250110848A1

公开(公告)日：2025-04-03

申请号：US18395390

申请日：2023-12-22

Applicant: Intel Corporation

Inventor： Ahmad Yasin ,  Andreas Kleen ,  Jonathan Combs

IPC: G06F11/34

Abstract: Techniques for performance monitoring are described. In certain examples, an apparatus (e.g., a processor) includes an execution circuit to execute one or more instructions; a performance monitoring counter; a control register comprising a threshold field; and a performance monitor control circuit to increment the performance monitoring counter in response to a performance monitoring event of the one or more instructions being equal to, but not greater than, the threshold field.

公开(公告)号：US12204430B2

公开(公告)日：2025-01-21

申请号：US17033746

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： Ahmad Yasin

IPC: G06F1/30 ,  G06F9/30 ,  G06F9/32 ,  G06F9/54 ,  G06F11/30 ,  G06F11/34

Abstract: Embodiments are disclosed for monitoring processor performance, including cost of events. In an embodiment, a processor includes a first counter, a second counter, a handler circuit, and an enable circuit. The first counter is to count occurrences of an event in the processor and to overflow upon the count of occurrences reaching a specified value. The second counter to measure a performance cost of the event. The handler circuit to generate and an event sampling record. The record is to include at least one value reflecting the performance cost. The enable circuit is to enable the handler circuit to generate the record.

公开(公告)号：US20240220388A1

公开(公告)日：2024-07-04

申请号：US18091975

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Baruch Chaikin ,  Ahmad Yasin

IPC: G06F11/34 ,  G06F9/455 ,  G06F9/50

CPC classification number: G06F11/3466 ,  G06F9/45533 ,  G06F9/5011 ,  G06F2201/88

Abstract: Techniques for flexible virtualization of performance monitoring are described. In an embodiment, an apparatus includes a plurality of performance monitoring hardware resources and an instruction decoder to decode a first instruction to access a first performance monitoring hardware resource of the plurality of performance monitoring hardware resources. In response to the first instruction being received by a virtual machine, the apparatus is to determine whether the first performance monitoring hardware resource is allocated to the virtual machine based on an allocation model to allow any set of the performance monitoring hardware resources to be allocated to the virtual machine, execute the first instruction within the virtual machine in response to a determination that the first performance monitoring hardware resource is allocated to the virtual machine, and raise an exception within the virtual machine in response to a determination that the first performance monitoring hardware resource is not allocated to the virtual machine.

公开(公告)号：US20240111656A1

公开(公告)日：2024-04-04

申请号：US17957978

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Ahmad Yasin ,  Anton Hanna ,  Yuval Alon ,  Amandeep Kaur

IPC: G06F11/34 ,  G06F9/30

CPC classification number: G06F11/3495 ,  G06F9/30145

Abstract: Techniques and mechanisms for circuitry of a processor to determine a count of prefetch instructions which have been retired, or are designated for retirement. In an embodiment, a performance monitoring unit (PMU) monitors the execution of an instruction sequence by a core of said processor. The PMU detects the retirement of a first instruction, and further makes a first determination that the instruction is of a prefetch instruction type. Based on the first determination, counter circuitry of the processor updates a count of one or more instruction retirements, wherein each such retired instruction is of the prefetch instruction type. The PMU further makes a second determination that another retired second instruction is of a non-prefetch instruction type. In another embodiment, the counter circuitry prevents any updating of that same count based on the second determination.

公开(公告)号：US11768683B2

公开(公告)日：2023-09-26

申请号：US17675962

申请日：2022-02-18

Applicant: Intel Corporation

Inventor： Ahmad Yasin

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/30

CPC classification number: G06F9/30076 ,  G06F9/3836 ,  G06F11/30

Abstract: A processor includes a front end, an execution unit, a retirement stage, a counter, and a performance monitoring unit. The front end includes logic to receive an event instruction to enable supervision of a front end event that will delay execution of instructions. The execution unit includes logic to set a register with parameters for supervision of the front end event. The front end further includes logic to receive a candidate instruction and match the candidate instruction to the front end event. The counter includes logic to generate the front end event upon retirement of the candidate instruction.

公开(公告)号：US11755442B2

公开(公告)日：2023-09-12

申请号：US17242018

申请日：2021-04-27

Applicant: Intel Corporation

Inventor： Ahmad Yasin

IPC: G06F11/30 ,  G06F11/34

CPC classification number: G06F11/3024 ,  G06F11/348 ,  G06F11/3409 ,  G06F11/3466 ,  G06F2201/88

Abstract: An apparatus and method are described for a multithreaded-aware performance monitor of a processor. For example, one embodiment of a processor comprises: one or more simultaneous multithreading cores to simultaneously execute multiple instruction threads; a plurality of performance monitor counters, each performance monitor counter to count baseline events during processing of the multiple instruction threads; and a performance monitor circuit to determine whether multiple threads are concurrently generating the same baseline event and, if so, then the performance monitor circuit to distribute the count of the baseline event for only one of the multiple threads in each processor cycle for which the multiple threads are active and the baseline event applies to.

公开(公告)号：US20220100626A1

公开(公告)日：2022-03-31

申请号：US17033746

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： Ahmad Yasin

IPC: G06F11/30 ,  G06F11/34 ,  G06F9/54 ,  G06F9/30 ,  G06F9/32

Abstract: Embodiments are disclosed for monitoring processor performance, including cost of events. In an embodiment, a processor includes a first counter, a second counter, a handler circuit, and an enable circuit. The first counter is to count occurrences of an event in the processor and to overflow upon the count of occurrences reaching a specified value. The second counter to measure a performance cost of the event. The handler circuit to generate and an event sampling record. The record is to include at least one value reflecting the performance cost. The enable circuit is to enable the handler circuit to generate the record.

公开(公告)号：US10969995B2

公开(公告)日：2021-04-06

申请号：US16161818

申请日：2018-10-16

Applicant: Intel Corporation

Inventor： Ahmad Yasin ,  Stanislav Bratanov

IPC: G06F3/06 ,  G06F12/0875 ,  G06F9/38 ,  G06F11/30 ,  G06F11/34 ,  G06F9/30

Abstract: Systems and method are disclosed for monitoring processor performance. Embodiments described relate to differentiating function performance by input parameters. In one embodiment, a method includes configuring a counter contained in a processor to count occurrences of an event in the processor and to overflow upon the count of occurrences reaching a specified value, configuring a precise event based sampling (PEBS) handler circuit to generate and store a PEBS record into a PEBS memory buffer after at least one overflow, the PEBS record containing at least one stack entry read from a stack after the at least one overflow, enabling the PEBS handler circuit to generate and store the PEBS record after the at least one overflow, generating and storing the PEBS record into the PEBS memory buffer after the at least one overflow; and storing contents of the PEBS memory buffer to a PEBS trace file in a memory.

公开(公告)号：US10909015B2

公开(公告)日：2021-02-02

申请号：US15396293

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Ahmad Yasin ,  Moshe Cohen ,  Jacob Jack Doweck

IPC: G06F11/30 ,  G06F9/46 ,  G06F11/34

Abstract: An apparatus and method are described for generating performance metrics of a processor. For example, one embodiment of a processor comprises: one or more simultaneous multithreading cores to simultaneously execute multiple instruction threads; a plurality of performance monitor counters, each to maintain a count of events occurring as a result of the execution of the multiple instruction threads; and a performance monitor unit to generate a plurality of performance metric values using the event counts stored in the performance monitor counters and in response to receipt of a request from software for the performance metric values.